Lines Matching +full:0 +full:x1eb
32 #size-cells = <0>;
34 CPU0: cpu@0 {
37 reg = <0x0 0x0>;
41 qcom,freq-domain = <&cpufreq_hw 0>;
64 reg = <0x0 0x100>;
68 qcom,freq-domain = <&cpufreq_hw 0>;
86 reg = <0x0 0x200>;
90 qcom,freq-domain = <&cpufreq_hw 0>;
108 reg = <0x0 0x300>;
112 qcom,freq-domain = <&cpufreq_hw 0>;
130 reg = <0x0 0x400>;
134 qcom,freq-domain = <&cpufreq_hw 0>;
152 reg = <0x0 0x500>;
156 qcom,freq-domain = <&cpufreq_hw 0>;
174 reg = <0x0 0x600>;
196 reg = <0x0 0x700>;
254 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
257 arm,psci-suspend-param = <0x40000004>;
264 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
267 arm,psci-suspend-param = <0x40000004>;
276 CLUSTER_SLEEP_0: cluster-sleep-0 {
278 arm,psci-suspend-param = <0x4100c244>;
295 reg = <0x0 0x80000000 0x0 0x0>;
408 #power-domain-cells = <0>;
414 #power-domain-cells = <0>;
420 #power-domain-cells = <0>;
426 #power-domain-cells = <0>;
432 #power-domain-cells = <0>;
438 #power-domain-cells = <0>;
444 #power-domain-cells = <0>;
450 #power-domain-cells = <0>;
456 #power-domain-cells = <0>;
467 reg = <0 0x85700000 0 0x600000>;
472 reg = <0 0x85e00000 0 0x100000>;
477 reg = <0 0x85fc0000 0 0x20000>;
483 reg = <0 0x85fe0000 0 0x20000>;
488 reg = <0 0x8ab00000 0 0x500000>;
493 reg = <0 0x8b000000 0 0x7e00000>;
498 reg = <0 0x92e00000 0 0x500000>;
503 reg = <0 0x93300000 0 0x100000>;
508 reg = <0 0x93400000 0 0x800000>;
513 reg = <0 0x93c00000 0 0x200000>;
518 reg = <0 0x93e00000 0 0x1e00000>;
523 reg = <0 0x95c00000 0 0x10000>;
528 reg = <0 0x95c10000 0 0x5000>;
533 reg = <0 0x95c15000 0 0x2000>;
538 reg = <0 0x97b00000 0 0x100000>;
543 reg = <0 0x9e400000 0 0x1400000>;
553 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
556 soc: soc@0 {
559 ranges = <0 0 0 0 0x10 0>;
560 dma-ranges = <0 0 0 0 0x10 0>;
565 reg = <0 0x00100000 0 0x1f0000>;
579 reg = <0 0x00784000 0 0x1000>;
584 reg = <0x1eb 0x1>;
591 reg = <0 0x007c4000 0 0x1000>,
592 <0 0x007c5000 0 0x1000>,
593 <0 0x007c8000 0 0x8000>;
606 interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>,
607 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>;
611 iommus = <&apps_smmu 0x140 0xf>;
614 pinctrl-0 = <&sdc1_state_on>;
659 reg = <0 0x00800000 0 0x60000>;
674 dma-channel-mask = <0xfa>;
675 iommus = <&apps_smmu 0x16 0x0>;
681 reg = <0 0x008c0000 0 0x6000>;
685 iommus = <&apps_smmu 0x3 0x0>;
689 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>;
695 reg = <0 0x00880000 0 0x4000>;
699 pinctrl-0 = <&qup_i2c0_default>;
702 #size-cells = <0>;
704 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
705 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
706 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
708 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
709 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
716 reg = <0 0x00884000 0 0x4000>;
720 pinctrl-0 = <&qup_i2c1_default>;
723 #size-cells = <0>;
725 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
726 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
727 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
729 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
737 reg = <0 0x00888000 0 0x4000>;
741 pinctrl-0 = <&qup_i2c2_default>;
744 #size-cells = <0>;
746 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
747 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
748 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
750 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
758 reg = <0 0x0088c000 0 0x4000>;
762 pinctrl-0 = <&qup_i2c3_default>;
765 #size-cells = <0>;
767 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
768 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
769 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
771 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
779 reg = <0 0x00890000 0 0x4000>;
783 pinctrl-0 = <&qup_i2c4_default>;
786 #size-cells = <0>;
788 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
789 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
790 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
792 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
800 reg = <0 0x00894000 0 0x4000>;
804 pinctrl-0 = <&qup_i2c5_default>;
807 #size-cells = <0>;
809 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
810 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
811 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
813 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
821 reg = <0 0x00898000 0 0x4000>;
825 pinctrl-0 = <&qup_i2c6_default>;
828 #size-cells = <0>;
830 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
831 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
832 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
834 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
842 reg = <0 0x0089c000 0 0x4000>;
846 pinctrl-0 = <&qup_i2c7_default>;
849 #size-cells = <0>;
851 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>,
852 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>,
853 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>;
855 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
865 reg = <0 0x00a00000 0 0x60000>;
880 dma-channel-mask = <0xfa>;
881 iommus = <&apps_smmu 0x6d6 0x0>;
887 reg = <0 0x00ac0000 0 0x6000>;
891 iommus = <&apps_smmu 0x6c3 0x0>;
895 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>;
901 reg = <0 0x00a80000 0 0x4000>;
905 pinctrl-0 = <&qup_i2c8_default>;
908 #size-cells = <0>;
910 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
911 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
912 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
914 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
915 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
922 reg = <0 0x00a84000 0 0x4000>;
926 pinctrl-0 = <&qup_i2c9_default>;
929 #size-cells = <0>;
931 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
932 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
933 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
935 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
943 reg = <0 0x00a88000 0 0x4000>;
947 pinctrl-0 = <&qup_i2c10_default>;
950 #size-cells = <0>;
952 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
953 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
954 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
956 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
964 reg = <0 0x00a8c000 0 0x4000>;
968 pinctrl-0 = <&qup_i2c11_default>;
971 #size-cells = <0>;
973 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
974 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
975 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
977 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
985 reg = <0 0x00a90000 0 0x4000>;
989 pinctrl-0 = <&qup_i2c12_default>;
992 #size-cells = <0>;
994 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
995 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
996 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
998 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1006 reg = <0 0x00a94000 0 0x4000>;
1010 pinctrl-0 = <&qup_i2c13_default>;
1013 #size-cells = <0>;
1015 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1016 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1017 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1019 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1027 reg = <0 0x00a98000 0 0x4000>;
1031 pinctrl-0 = <&qup_i2c14_default>;
1034 #size-cells = <0>;
1036 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1037 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1038 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1040 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1048 reg = <0 0x00a9c000 0 0x4000>;
1052 pinctrl-0 = <&qup_i2c15_default>;
1055 #size-cells = <0>;
1057 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>,
1058 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>,
1059 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>;
1061 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1070 reg = <0 0x01380000 0 0x27200>;
1077 reg = <0 0x014e0000 0 0x400>;
1084 reg = <0 0x01500000 0 0x5080>;
1091 reg = <0 0x01620000 0 0x18080>;
1098 reg = <0 0x016e0000 0 0x15080>;
1105 reg = <0 0x01700000 0 0x1f300>;
1112 reg = <0 0x01740000 0 0x1c100>;
1119 reg = <0 0x03400000 0 0xc00000>;
1125 gpio-ranges = <&tlmm 0 0 151>;
1261 reg = <0 0x088e2000 0 0x400>;
1262 #phy-cells = <0>;
1277 reg = <0 0x0a6f8800 0 0x400>;
1309 interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>,
1310 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>;
1317 reg = <0 0x0a600000 0 0xcd00>;
1319 iommus = <&apps_smmu 0x740 0>;
1329 reg = <0 0x0b220000 0 0x30000>;
1330 qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>,
1340 reg = <0 0x0c440000 0 0x1100>,
1341 <0 0x0c600000 0 0x2000000>,
1342 <0 0x0e600000 0 0x100000>,
1343 <0 0x0e700000 0 0xa0000>,
1344 <0 0x0c40a000 0 0x26000>;
1348 qcom,ee = <0>;
1349 qcom,channel = <0>;
1351 #size-cells = <0>;
1358 reg = <0 0x15000000 0 0x80000>;
1430 reg = <0 0x17900000 0 0xd080>;
1437 reg = <0 0x179c0000 0 0x10000>,
1438 <0 0x179d0000 0 0x10000>,
1439 <0 0x179e0000 0 0x10000>;
1440 reg-names = "drv-0", "drv-1", "drv-2";
1445 qcom,tcs-offset = <0xd00>;
1517 reg = <0 0x17a00000 0 0x10000>, /* GICD */
1518 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
1526 reg = <0 0x17d41000 0 0x1400>;
1536 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;