Lines Matching +full:dmic01 +full:- +full:state
1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
7 #include <dt-bindings/clock/qcom,camcc-sc7280.h>
8 #include <dt-bindings/clock/qcom,dispcc-sc7280.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7280.h>
11 #include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h>
12 #include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h>
13 #include <dt-bindings/clock/qcom,rpmh.h>
14 #include <dt-bindings/clock/qcom,videocc-sc7280.h>
15 #include <dt-bindings/dma/qcom-gpi.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interconnect/qcom,osm-l3.h>
18 #include <dt-bindings/interconnect/qcom,sc7280.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 #include <dt-bindings/mailbox/qcom-ipcc.h>
21 #include <dt-bindings/phy/phy-qcom-qmp.h>
22 #include <dt-bindings/power/qcom-rpmpd.h>
23 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
24 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
25 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
26 #include <dt-bindings/sound/qcom,lpass.h>
27 #include <dt-bindings/thermal/thermal.h>
30 interrupt-parent = <&intc>;
32 #address-cells = <2>;
33 #size-cells = <2>;
75 xo_board: xo-board {
76 compatible = "fixed-clock";
77 clock-frequency = <76800000>;
78 #clock-cells = <0>;
81 sleep_clk: sleep-clk {
82 compatible = "fixed-clock";
83 clock-frequency = <32000>;
84 #clock-cells = <0>;
88 reserved-memory {
89 #address-cells = <2>;
90 #size-cells = <2>;
94 no-map;
100 no-map;
105 no-map;
110 no-map;
115 compatible = "qcom,cmd-db";
116 no-map;
121 no-map;
126 no-map;
131 no-map;
135 no-map;
141 no-map;
146 no-map;
151 no-map;
155 compatible = "qcom,rmtfs-mem";
157 no-map;
159 qcom,client-id = <1>;
165 #address-cells = <2>;
166 #size-cells = <0>;
173 enable-method = "psci";
174 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
177 next-level-cache = <&L2_0>;
178 operating-points-v2 = <&cpu0_opp_table>;
181 qcom,freq-domain = <&cpufreq_hw 0>;
182 #cooling-cells = <2>;
183 L2_0: l2-cache {
185 cache-level = <2>;
186 cache-unified;
187 next-level-cache = <&L3_0>;
188 L3_0: l3-cache {
190 cache-level = <3>;
191 cache-unified;
201 enable-method = "psci";
202 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
205 next-level-cache = <&L2_100>;
206 operating-points-v2 = <&cpu0_opp_table>;
209 qcom,freq-domain = <&cpufreq_hw 0>;
210 #cooling-cells = <2>;
211 L2_100: l2-cache {
213 cache-level = <2>;
214 cache-unified;
215 next-level-cache = <&L3_0>;
224 enable-method = "psci";
225 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
228 next-level-cache = <&L2_200>;
229 operating-points-v2 = <&cpu0_opp_table>;
232 qcom,freq-domain = <&cpufreq_hw 0>;
233 #cooling-cells = <2>;
234 L2_200: l2-cache {
236 cache-level = <2>;
237 cache-unified;
238 next-level-cache = <&L3_0>;
247 enable-method = "psci";
248 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
251 next-level-cache = <&L2_300>;
252 operating-points-v2 = <&cpu0_opp_table>;
255 qcom,freq-domain = <&cpufreq_hw 0>;
256 #cooling-cells = <2>;
257 L2_300: l2-cache {
259 cache-level = <2>;
260 cache-unified;
261 next-level-cache = <&L3_0>;
270 enable-method = "psci";
271 cpu-idle-states = <&BIG_CPU_SLEEP_0
274 next-level-cache = <&L2_400>;
275 operating-points-v2 = <&cpu4_opp_table>;
278 qcom,freq-domain = <&cpufreq_hw 1>;
279 #cooling-cells = <2>;
280 L2_400: l2-cache {
282 cache-level = <2>;
283 cache-unified;
284 next-level-cache = <&L3_0>;
293 enable-method = "psci";
294 cpu-idle-states = <&BIG_CPU_SLEEP_0
297 next-level-cache = <&L2_500>;
298 operating-points-v2 = <&cpu4_opp_table>;
301 qcom,freq-domain = <&cpufreq_hw 1>;
302 #cooling-cells = <2>;
303 L2_500: l2-cache {
305 cache-level = <2>;
306 cache-unified;
307 next-level-cache = <&L3_0>;
316 enable-method = "psci";
317 cpu-idle-states = <&BIG_CPU_SLEEP_0
320 next-level-cache = <&L2_600>;
321 operating-points-v2 = <&cpu4_opp_table>;
324 qcom,freq-domain = <&cpufreq_hw 1>;
325 #cooling-cells = <2>;
326 L2_600: l2-cache {
328 cache-level = <2>;
329 cache-unified;
330 next-level-cache = <&L3_0>;
339 enable-method = "psci";
340 cpu-idle-states = <&BIG_CPU_SLEEP_0
343 next-level-cache = <&L2_700>;
344 operating-points-v2 = <&cpu7_opp_table>;
347 qcom,freq-domain = <&cpufreq_hw 2>;
348 #cooling-cells = <2>;
349 L2_700: l2-cache {
351 cache-level = <2>;
352 cache-unified;
353 next-level-cache = <&L3_0>;
357 cpu-map {
393 idle-states {
394 entry-method = "psci";
396 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
397 compatible = "arm,idle-state";
398 idle-state-name = "little-power-down";
399 arm,psci-suspend-param = <0x40000003>;
400 entry-latency-us = <549>;
401 exit-latency-us = <901>;
402 min-residency-us = <1774>;
403 local-timer-stop;
406 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
407 compatible = "arm,idle-state";
408 idle-state-name = "little-rail-power-down";
409 arm,psci-suspend-param = <0x40000004>;
410 entry-latency-us = <702>;
411 exit-latency-us = <915>;
412 min-residency-us = <4001>;
413 local-timer-stop;
416 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
417 compatible = "arm,idle-state";
418 idle-state-name = "big-power-down";
419 arm,psci-suspend-param = <0x40000003>;
420 entry-latency-us = <523>;
421 exit-latency-us = <1244>;
422 min-residency-us = <2207>;
423 local-timer-stop;
426 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
427 compatible = "arm,idle-state";
428 idle-state-name = "big-rail-power-down";
429 arm,psci-suspend-param = <0x40000004>;
430 entry-latency-us = <526>;
431 exit-latency-us = <1854>;
432 min-residency-us = <5555>;
433 local-timer-stop;
436 CLUSTER_SLEEP_0: cluster-sleep-0 {
437 compatible = "arm,idle-state";
438 idle-state-name = "cluster-power-down";
439 arm,psci-suspend-param = <0x40003444>;
440 entry-latency-us = <3263>;
441 exit-latency-us = <6562>;
442 min-residency-us = <9926>;
443 local-timer-stop;
448 cpu0_opp_table: opp-table-cpu0 {
449 compatible = "operating-points-v2";
450 opp-shared;
452 cpu0_opp_300mhz: opp-300000000 {
453 opp-hz = /bits/ 64 <300000000>;
454 opp-peak-kBps = <800000 9600000>;
457 cpu0_opp_691mhz: opp-691200000 {
458 opp-hz = /bits/ 64 <691200000>;
459 opp-peak-kBps = <800000 17817600>;
462 cpu0_opp_806mhz: opp-806400000 {
463 opp-hz = /bits/ 64 <806400000>;
464 opp-peak-kBps = <800000 20889600>;
467 cpu0_opp_941mhz: opp-940800000 {
468 opp-hz = /bits/ 64 <940800000>;
469 opp-peak-kBps = <1804000 24576000>;
472 cpu0_opp_1152mhz: opp-1152000000 {
473 opp-hz = /bits/ 64 <1152000000>;
474 opp-peak-kBps = <2188000 27033600>;
477 cpu0_opp_1325mhz: opp-1324800000 {
478 opp-hz = /bits/ 64 <1324800000>;
479 opp-peak-kBps = <2188000 33792000>;
482 cpu0_opp_1517mhz: opp-1516800000 {
483 opp-hz = /bits/ 64 <1516800000>;
484 opp-peak-kBps = <3072000 38092800>;
487 cpu0_opp_1651mhz: opp-1651200000 {
488 opp-hz = /bits/ 64 <1651200000>;
489 opp-peak-kBps = <3072000 41779200>;
492 cpu0_opp_1805mhz: opp-1804800000 {
493 opp-hz = /bits/ 64 <1804800000>;
494 opp-peak-kBps = <4068000 48537600>;
497 cpu0_opp_1958mhz: opp-1958400000 {
498 opp-hz = /bits/ 64 <1958400000>;
499 opp-peak-kBps = <4068000 48537600>;
502 cpu0_opp_2016mhz: opp-2016000000 {
503 opp-hz = /bits/ 64 <2016000000>;
504 opp-peak-kBps = <6220000 48537600>;
508 cpu4_opp_table: opp-table-cpu4 {
509 compatible = "operating-points-v2";
510 opp-shared;
512 cpu4_opp_691mhz: opp-691200000 {
513 opp-hz = /bits/ 64 <691200000>;
514 opp-peak-kBps = <1804000 9600000>;
517 cpu4_opp_941mhz: opp-940800000 {
518 opp-hz = /bits/ 64 <940800000>;
519 opp-peak-kBps = <2188000 17817600>;
522 cpu4_opp_1229mhz: opp-1228800000 {
523 opp-hz = /bits/ 64 <1228800000>;
524 opp-peak-kBps = <4068000 24576000>;
527 cpu4_opp_1344mhz: opp-1344000000 {
528 opp-hz = /bits/ 64 <1344000000>;
529 opp-peak-kBps = <4068000 24576000>;
532 cpu4_opp_1517mhz: opp-1516800000 {
533 opp-hz = /bits/ 64 <1516800000>;
534 opp-peak-kBps = <4068000 24576000>;
537 cpu4_opp_1651mhz: opp-1651200000 {
538 opp-hz = /bits/ 64 <1651200000>;
539 opp-peak-kBps = <6220000 38092800>;
542 cpu4_opp_1901mhz: opp-1900800000 {
543 opp-hz = /bits/ 64 <1900800000>;
544 opp-peak-kBps = <6220000 44851200>;
547 cpu4_opp_2054mhz: opp-2054400000 {
548 opp-hz = /bits/ 64 <2054400000>;
549 opp-peak-kBps = <6220000 44851200>;
552 cpu4_opp_2112mhz: opp-2112000000 {
553 opp-hz = /bits/ 64 <2112000000>;
554 opp-peak-kBps = <6220000 44851200>;
557 cpu4_opp_2131mhz: opp-2131200000 {
558 opp-hz = /bits/ 64 <2131200000>;
559 opp-peak-kBps = <6220000 44851200>;
562 cpu4_opp_2208mhz: opp-2208000000 {
563 opp-hz = /bits/ 64 <2208000000>;
564 opp-peak-kBps = <6220000 44851200>;
567 cpu4_opp_2400mhz: opp-2400000000 {
568 opp-hz = /bits/ 64 <2400000000>;
569 opp-peak-kBps = <8532000 48537600>;
572 cpu4_opp_2611mhz: opp-2611200000 {
573 opp-hz = /bits/ 64 <2611200000>;
574 opp-peak-kBps = <8532000 48537600>;
578 cpu7_opp_table: opp-table-cpu7 {
579 compatible = "operating-points-v2";
580 opp-shared;
582 cpu7_opp_806mhz: opp-806400000 {
583 opp-hz = /bits/ 64 <806400000>;
584 opp-peak-kBps = <1804000 9600000>;
587 cpu7_opp_1056mhz: opp-1056000000 {
588 opp-hz = /bits/ 64 <1056000000>;
589 opp-peak-kBps = <2188000 17817600>;
592 cpu7_opp_1325mhz: opp-1324800000 {
593 opp-hz = /bits/ 64 <1324800000>;
594 opp-peak-kBps = <4068000 24576000>;
597 cpu7_opp_1517mhz: opp-1516800000 {
598 opp-hz = /bits/ 64 <1516800000>;
599 opp-peak-kBps = <4068000 24576000>;
602 cpu7_opp_1766mhz: opp-1766400000 {
603 opp-hz = /bits/ 64 <1766400000>;
604 opp-peak-kBps = <6220000 38092800>;
607 cpu7_opp_1862mhz: opp-1862400000 {
608 opp-hz = /bits/ 64 <1862400000>;
609 opp-peak-kBps = <6220000 38092800>;
612 cpu7_opp_2035mhz: opp-2035200000 {
613 opp-hz = /bits/ 64 <2035200000>;
614 opp-peak-kBps = <6220000 38092800>;
617 cpu7_opp_2112mhz: opp-2112000000 {
618 opp-hz = /bits/ 64 <2112000000>;
619 opp-peak-kBps = <6220000 44851200>;
622 cpu7_opp_2208mhz: opp-2208000000 {
623 opp-hz = /bits/ 64 <2208000000>;
624 opp-peak-kBps = <6220000 44851200>;
627 cpu7_opp_2381mhz: opp-2380800000 {
628 opp-hz = /bits/ 64 <2380800000>;
629 opp-peak-kBps = <6832000 44851200>;
632 cpu7_opp_2400mhz: opp-2400000000 {
633 opp-hz = /bits/ 64 <2400000000>;
634 opp-peak-kBps = <8532000 48537600>;
637 cpu7_opp_2515mhz: opp-2515200000 {
638 opp-hz = /bits/ 64 <2515200000>;
639 opp-peak-kBps = <8532000 48537600>;
642 cpu7_opp_2707mhz: opp-2707200000 {
643 opp-hz = /bits/ 64 <2707200000>;
644 opp-peak-kBps = <8532000 48537600>;
647 cpu7_opp_3014mhz: opp-3014400000 {
648 opp-hz = /bits/ 64 <3014400000>;
649 opp-peak-kBps = <8532000 48537600>;
661 compatible = "qcom,scm-sc7280", "qcom,scm";
666 compatible = "qcom,sc7280-clk-virt";
667 #interconnect-cells = <2>;
668 qcom,bcm-voters = <&apps_bcm_voter>;
673 memory-region = <&smem_mem>;
677 smp2p-adsp {
680 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
686 qcom,local-pid = <0>;
687 qcom,remote-pid = <2>;
689 adsp_smp2p_out: master-kernel {
690 qcom,entry-name = "master-kernel";
691 #qcom,smem-state-cells = <1>;
694 adsp_smp2p_in: slave-kernel {
695 qcom,entry-name = "slave-kernel";
696 interrupt-controller;
697 #interrupt-cells = <2>;
701 smp2p-cdsp {
704 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
710 qcom,local-pid = <0>;
711 qcom,remote-pid = <5>;
713 cdsp_smp2p_out: master-kernel {
714 qcom,entry-name = "master-kernel";
715 #qcom,smem-state-cells = <1>;
718 cdsp_smp2p_in: slave-kernel {
719 qcom,entry-name = "slave-kernel";
720 interrupt-controller;
721 #interrupt-cells = <2>;
725 smp2p-mpss {
728 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
734 qcom,local-pid = <0>;
735 qcom,remote-pid = <1>;
737 modem_smp2p_out: master-kernel {
738 qcom,entry-name = "master-kernel";
739 #qcom,smem-state-cells = <1>;
742 modem_smp2p_in: slave-kernel {
743 qcom,entry-name = "slave-kernel";
744 interrupt-controller;
745 #interrupt-cells = <2>;
748 ipa_smp2p_out: ipa-ap-to-modem {
749 qcom,entry-name = "ipa";
750 #qcom,smem-state-cells = <1>;
753 ipa_smp2p_in: ipa-modem-to-ap {
754 qcom,entry-name = "ipa";
755 interrupt-controller;
756 #interrupt-cells = <2>;
760 smp2p-wpss {
763 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
769 qcom,local-pid = <0>;
770 qcom,remote-pid = <13>;
772 wpss_smp2p_out: master-kernel {
773 qcom,entry-name = "master-kernel";
774 #qcom,smem-state-cells = <1>;
777 wpss_smp2p_in: slave-kernel {
778 qcom,entry-name = "slave-kernel";
779 interrupt-controller;
780 #interrupt-cells = <2>;
783 wlan_smp2p_out: wlan-ap-to-wpss {
784 qcom,entry-name = "wlan";
785 #qcom,smem-state-cells = <1>;
788 wlan_smp2p_in: wlan-wpss-to-ap {
789 qcom,entry-name = "wlan";
790 interrupt-controller;
791 #interrupt-cells = <2>;
796 compatible = "arm,armv8-pmuv3";
801 compatible = "arm,psci-1.0";
805 qspi_opp_table: opp-table-qspi {
806 compatible = "operating-points-v2";
808 opp-75000000 {
809 opp-hz = /bits/ 64 <75000000>;
810 required-opps = <&rpmhpd_opp_low_svs>;
813 opp-150000000 {
814 opp-hz = /bits/ 64 <150000000>;
815 required-opps = <&rpmhpd_opp_svs>;
818 opp-200000000 {
819 opp-hz = /bits/ 64 <200000000>;
820 required-opps = <&rpmhpd_opp_svs_l1>;
823 opp-300000000 {
824 opp-hz = /bits/ 64 <300000000>;
825 required-opps = <&rpmhpd_opp_nom>;
829 qup_opp_table: opp-table-qup {
830 compatible = "operating-points-v2";
832 opp-75000000 {
833 opp-hz = /bits/ 64 <75000000>;
834 required-opps = <&rpmhpd_opp_low_svs>;
837 opp-100000000 {
838 opp-hz = /bits/ 64 <100000000>;
839 required-opps = <&rpmhpd_opp_svs>;
842 opp-128000000 {
843 opp-hz = /bits/ 64 <128000000>;
844 required-opps = <&rpmhpd_opp_nom>;
849 #address-cells = <2>;
850 #size-cells = <2>;
852 dma-ranges = <0 0 0 0 0x10 0>;
853 compatible = "simple-bus";
855 gcc: clock-controller@100000 {
856 compatible = "qcom,gcc-sc7280";
863 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk",
868 #clock-cells = <1>;
869 #reset-cells = <1>;
870 #power-domain-cells = <1>;
871 power-domains = <&rpmhpd SC7280_CX>;
875 compatible = "qcom,sc7280-ipcc", "qcom,ipcc";
878 interrupt-controller;
879 #interrupt-cells = <3>;
880 #mbox-cells = <2>;
884 compatible = "qcom,sc7280-qfprom", "qcom,qfprom";
890 clock-names = "core";
891 power-domains = <&rpmhpd SC7280_MX>;
892 #address-cells = <1>;
893 #size-cells = <1>;
902 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
903 pinctrl-names = "default", "sleep";
904 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
905 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
910 reg-names = "hc", "cqhci";
915 interrupt-names = "hc_irq", "pwr_irq";
920 clock-names = "iface", "core", "xo";
923 interconnect-names = "sdhc-ddr","cpu-sdhc";
924 power-domains = <&rpmhpd SC7280_CX>;
925 operating-points-v2 = <&sdhc1_opp_table>;
927 bus-width = <8>;
928 supports-cqe;
929 dma-coherent;
931 qcom,dll-config = <0x0007642c>;
932 qcom,ddr-config = <0x80040868>;
934 mmc-ddr-1_8v;
935 mmc-hs200-1_8v;
936 mmc-hs400-1_8v;
937 mmc-hs400-enhanced-strobe;
941 sdhc1_opp_table: opp-table {
942 compatible = "operating-points-v2";
944 opp-100000000 {
945 opp-hz = /bits/ 64 <100000000>;
946 required-opps = <&rpmhpd_opp_low_svs>;
947 opp-peak-kBps = <1800000 400000>;
948 opp-avg-kBps = <100000 0>;
951 opp-384000000 {
952 opp-hz = /bits/ 64 <384000000>;
953 required-opps = <&rpmhpd_opp_nom>;
954 opp-peak-kBps = <5400000 1600000>;
955 opp-avg-kBps = <390000 0>;
960 gpi_dma0: dma-controller@900000 {
961 #dma-cells = <3>;
962 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
976 dma-channels = <12>;
977 dma-channel-mask = <0x7f>;
983 compatible = "qcom,geni-se-qup";
987 clock-names = "m-ahb", "s-ahb";
988 #address-cells = <2>;
989 #size-cells = <2>;
995 compatible = "qcom,geni-i2c";
998 clock-names = "se";
999 pinctrl-names = "default";
1000 pinctrl-0 = <&qup_i2c0_data_clk>;
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1007 interconnect-names = "qup-core", "qup-config",
1008 "qup-memory";
1009 power-domains = <&rpmhpd SC7280_CX>;
1010 required-opps = <&rpmhpd_opp_low_svs>;
1013 dma-names = "tx", "rx";
1018 compatible = "qcom,geni-spi";
1021 clock-names = "se";
1022 pinctrl-names = "default";
1023 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1025 #address-cells = <1>;
1026 #size-cells = <0>;
1027 power-domains = <&rpmhpd SC7280_CX>;
1028 operating-points-v2 = <&qup_opp_table>;
1031 interconnect-names = "qup-core", "qup-config";
1034 dma-names = "tx", "rx";
1039 compatible = "qcom,geni-uart";
1042 clock-names = "se";
1043 pinctrl-names = "default";
1044 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1046 power-domains = <&rpmhpd SC7280_CX>;
1047 operating-points-v2 = <&qup_opp_table>;
1050 interconnect-names = "qup-core", "qup-config";
1055 compatible = "qcom,geni-i2c";
1058 clock-names = "se";
1059 pinctrl-names = "default";
1060 pinctrl-0 = <&qup_i2c1_data_clk>;
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1067 interconnect-names = "qup-core", "qup-config",
1068 "qup-memory";
1069 power-domains = <&rpmhpd SC7280_CX>;
1070 required-opps = <&rpmhpd_opp_low_svs>;
1073 dma-names = "tx", "rx";
1078 compatible = "qcom,geni-spi";
1081 clock-names = "se";
1082 pinctrl-names = "default";
1083 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1085 #address-cells = <1>;
1086 #size-cells = <0>;
1087 power-domains = <&rpmhpd SC7280_CX>;
1088 operating-points-v2 = <&qup_opp_table>;
1091 interconnect-names = "qup-core", "qup-config";
1094 dma-names = "tx", "rx";
1099 compatible = "qcom,geni-uart";
1102 clock-names = "se";
1103 pinctrl-names = "default";
1104 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1106 power-domains = <&rpmhpd SC7280_CX>;
1107 operating-points-v2 = <&qup_opp_table>;
1110 interconnect-names = "qup-core", "qup-config";
1115 compatible = "qcom,geni-i2c";
1118 clock-names = "se";
1119 pinctrl-names = "default";
1120 pinctrl-0 = <&qup_i2c2_data_clk>;
1122 #address-cells = <1>;
1123 #size-cells = <0>;
1127 interconnect-names = "qup-core", "qup-config",
1128 "qup-memory";
1129 power-domains = <&rpmhpd SC7280_CX>;
1130 required-opps = <&rpmhpd_opp_low_svs>;
1133 dma-names = "tx", "rx";
1138 compatible = "qcom,geni-spi";
1141 clock-names = "se";
1142 pinctrl-names = "default";
1143 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1145 #address-cells = <1>;
1146 #size-cells = <0>;
1147 power-domains = <&rpmhpd SC7280_CX>;
1148 operating-points-v2 = <&qup_opp_table>;
1151 interconnect-names = "qup-core", "qup-config";
1154 dma-names = "tx", "rx";
1159 compatible = "qcom,geni-uart";
1162 clock-names = "se";
1163 pinctrl-names = "default";
1164 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1166 power-domains = <&rpmhpd SC7280_CX>;
1167 operating-points-v2 = <&qup_opp_table>;
1170 interconnect-names = "qup-core", "qup-config";
1175 compatible = "qcom,geni-i2c";
1178 clock-names = "se";
1179 pinctrl-names = "default";
1180 pinctrl-0 = <&qup_i2c3_data_clk>;
1182 #address-cells = <1>;
1183 #size-cells = <0>;
1187 interconnect-names = "qup-core", "qup-config",
1188 "qup-memory";
1189 power-domains = <&rpmhpd SC7280_CX>;
1190 required-opps = <&rpmhpd_opp_low_svs>;
1193 dma-names = "tx", "rx";
1198 compatible = "qcom,geni-spi";
1201 clock-names = "se";
1202 pinctrl-names = "default";
1203 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1207 power-domains = <&rpmhpd SC7280_CX>;
1208 operating-points-v2 = <&qup_opp_table>;
1211 interconnect-names = "qup-core", "qup-config";
1214 dma-names = "tx", "rx";
1219 compatible = "qcom,geni-uart";
1222 clock-names = "se";
1223 pinctrl-names = "default";
1224 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1226 power-domains = <&rpmhpd SC7280_CX>;
1227 operating-points-v2 = <&qup_opp_table>;
1230 interconnect-names = "qup-core", "qup-config";
1235 compatible = "qcom,geni-i2c";
1238 clock-names = "se";
1239 pinctrl-names = "default";
1240 pinctrl-0 = <&qup_i2c4_data_clk>;
1242 #address-cells = <1>;
1243 #size-cells = <0>;
1247 interconnect-names = "qup-core", "qup-config",
1248 "qup-memory";
1249 power-domains = <&rpmhpd SC7280_CX>;
1250 required-opps = <&rpmhpd_opp_low_svs>;
1253 dma-names = "tx", "rx";
1258 compatible = "qcom,geni-spi";
1261 clock-names = "se";
1262 pinctrl-names = "default";
1263 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1265 #address-cells = <1>;
1266 #size-cells = <0>;
1267 power-domains = <&rpmhpd SC7280_CX>;
1268 operating-points-v2 = <&qup_opp_table>;
1271 interconnect-names = "qup-core", "qup-config";
1274 dma-names = "tx", "rx";
1279 compatible = "qcom,geni-uart";
1282 clock-names = "se";
1283 pinctrl-names = "default";
1284 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1286 power-domains = <&rpmhpd SC7280_CX>;
1287 operating-points-v2 = <&qup_opp_table>;
1290 interconnect-names = "qup-core", "qup-config";
1295 compatible = "qcom,geni-i2c";
1298 clock-names = "se";
1299 pinctrl-names = "default";
1300 pinctrl-0 = <&qup_i2c5_data_clk>;
1302 #address-cells = <1>;
1303 #size-cells = <0>;
1307 interconnect-names = "qup-core", "qup-config",
1308 "qup-memory";
1309 power-domains = <&rpmhpd SC7280_CX>;
1310 required-opps = <&rpmhpd_opp_low_svs>;
1313 dma-names = "tx", "rx";
1318 compatible = "qcom,geni-spi";
1321 clock-names = "se";
1322 pinctrl-names = "default";
1323 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1325 #address-cells = <1>;
1326 #size-cells = <0>;
1327 power-domains = <&rpmhpd SC7280_CX>;
1328 operating-points-v2 = <&qup_opp_table>;
1331 interconnect-names = "qup-core", "qup-config";
1334 dma-names = "tx", "rx";
1339 compatible = "qcom,geni-uart";
1342 clock-names = "se";
1343 pinctrl-names = "default";
1344 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
1346 power-domains = <&rpmhpd SC7280_CX>;
1347 operating-points-v2 = <&qup_opp_table>;
1350 interconnect-names = "qup-core", "qup-config";
1355 compatible = "qcom,geni-i2c";
1358 clock-names = "se";
1359 pinctrl-names = "default";
1360 pinctrl-0 = <&qup_i2c6_data_clk>;
1362 #address-cells = <1>;
1363 #size-cells = <0>;
1367 interconnect-names = "qup-core", "qup-config",
1368 "qup-memory";
1369 power-domains = <&rpmhpd SC7280_CX>;
1370 required-opps = <&rpmhpd_opp_low_svs>;
1373 dma-names = "tx", "rx";
1378 compatible = "qcom,geni-spi";
1381 clock-names = "se";
1382 pinctrl-names = "default";
1383 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1385 #address-cells = <1>;
1386 #size-cells = <0>;
1387 power-domains = <&rpmhpd SC7280_CX>;
1388 operating-points-v2 = <&qup_opp_table>;
1391 interconnect-names = "qup-core", "qup-config";
1394 dma-names = "tx", "rx";
1399 compatible = "qcom,geni-uart";
1402 clock-names = "se";
1403 pinctrl-names = "default";
1404 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1406 power-domains = <&rpmhpd SC7280_CX>;
1407 operating-points-v2 = <&qup_opp_table>;
1410 interconnect-names = "qup-core", "qup-config";
1415 compatible = "qcom,geni-i2c";
1418 clock-names = "se";
1419 pinctrl-names = "default";
1420 pinctrl-0 = <&qup_i2c7_data_clk>;
1422 #address-cells = <1>;
1423 #size-cells = <0>;
1427 interconnect-names = "qup-core", "qup-config",
1428 "qup-memory";
1429 power-domains = <&rpmhpd SC7280_CX>;
1430 required-opps = <&rpmhpd_opp_low_svs>;
1433 dma-names = "tx", "rx";
1438 compatible = "qcom,geni-spi";
1441 clock-names = "se";
1442 pinctrl-names = "default";
1443 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1445 #address-cells = <1>;
1446 #size-cells = <0>;
1447 power-domains = <&rpmhpd SC7280_CX>;
1448 operating-points-v2 = <&qup_opp_table>;
1451 interconnect-names = "qup-core", "qup-config";
1454 dma-names = "tx", "rx";
1459 compatible = "qcom,geni-uart";
1462 clock-names = "se";
1463 pinctrl-names = "default";
1464 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1466 power-domains = <&rpmhpd SC7280_CX>;
1467 operating-points-v2 = <&qup_opp_table>;
1470 interconnect-names = "qup-core", "qup-config";
1475 gpi_dma1: dma-controller@a00000 {
1476 #dma-cells = <3>;
1477 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
1491 dma-channels = <12>;
1492 dma-channel-mask = <0x1e>;
1498 compatible = "qcom,geni-se-qup";
1502 clock-names = "m-ahb", "s-ahb";
1503 #address-cells = <2>;
1504 #size-cells = <2>;
1510 compatible = "qcom,geni-i2c";
1513 clock-names = "se";
1514 pinctrl-names = "default";
1515 pinctrl-0 = <&qup_i2c8_data_clk>;
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1522 interconnect-names = "qup-core", "qup-config",
1523 "qup-memory";
1524 power-domains = <&rpmhpd SC7280_CX>;
1525 required-opps = <&rpmhpd_opp_low_svs>;
1528 dma-names = "tx", "rx";
1533 compatible = "qcom,geni-spi";
1536 clock-names = "se";
1537 pinctrl-names = "default";
1538 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1540 #address-cells = <1>;
1541 #size-cells = <0>;
1542 power-domains = <&rpmhpd SC7280_CX>;
1543 operating-points-v2 = <&qup_opp_table>;
1546 interconnect-names = "qup-core", "qup-config";
1549 dma-names = "tx", "rx";
1554 compatible = "qcom,geni-uart";
1557 clock-names = "se";
1558 pinctrl-names = "default";
1559 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1561 power-domains = <&rpmhpd SC7280_CX>;
1562 operating-points-v2 = <&qup_opp_table>;
1565 interconnect-names = "qup-core", "qup-config";
1570 compatible = "qcom,geni-i2c";
1573 clock-names = "se";
1574 pinctrl-names = "default";
1575 pinctrl-0 = <&qup_i2c9_data_clk>;
1577 #address-cells = <1>;
1578 #size-cells = <0>;
1582 interconnect-names = "qup-core", "qup-config",
1583 "qup-memory";
1584 power-domains = <&rpmhpd SC7280_CX>;
1585 required-opps = <&rpmhpd_opp_low_svs>;
1588 dma-names = "tx", "rx";
1593 compatible = "qcom,geni-spi";
1596 clock-names = "se";
1597 pinctrl-names = "default";
1598 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1600 #address-cells = <1>;
1601 #size-cells = <0>;
1602 power-domains = <&rpmhpd SC7280_CX>;
1603 operating-points-v2 = <&qup_opp_table>;
1606 interconnect-names = "qup-core", "qup-config";
1609 dma-names = "tx", "rx";
1614 compatible = "qcom,geni-uart";
1617 clock-names = "se";
1618 pinctrl-names = "default";
1619 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1621 power-domains = <&rpmhpd SC7280_CX>;
1622 operating-points-v2 = <&qup_opp_table>;
1625 interconnect-names = "qup-core", "qup-config";
1630 compatible = "qcom,geni-i2c";
1633 clock-names = "se";
1634 pinctrl-names = "default";
1635 pinctrl-0 = <&qup_i2c10_data_clk>;
1637 #address-cells = <1>;
1638 #size-cells = <0>;
1642 interconnect-names = "qup-core", "qup-config",
1643 "qup-memory";
1644 power-domains = <&rpmhpd SC7280_CX>;
1645 required-opps = <&rpmhpd_opp_low_svs>;
1648 dma-names = "tx", "rx";
1653 compatible = "qcom,geni-spi";
1656 clock-names = "se";
1657 pinctrl-names = "default";
1658 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1660 #address-cells = <1>;
1661 #size-cells = <0>;
1662 power-domains = <&rpmhpd SC7280_CX>;
1663 operating-points-v2 = <&qup_opp_table>;
1666 interconnect-names = "qup-core", "qup-config";
1669 dma-names = "tx", "rx";
1674 compatible = "qcom,geni-uart";
1677 clock-names = "se";
1678 pinctrl-names = "default";
1679 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1681 power-domains = <&rpmhpd SC7280_CX>;
1682 operating-points-v2 = <&qup_opp_table>;
1685 interconnect-names = "qup-core", "qup-config";
1690 compatible = "qcom,geni-i2c";
1693 clock-names = "se";
1694 pinctrl-names = "default";
1695 pinctrl-0 = <&qup_i2c11_data_clk>;
1697 #address-cells = <1>;
1698 #size-cells = <0>;
1702 interconnect-names = "qup-core", "qup-config",
1703 "qup-memory";
1704 power-domains = <&rpmhpd SC7280_CX>;
1705 required-opps = <&rpmhpd_opp_low_svs>;
1708 dma-names = "tx", "rx";
1713 compatible = "qcom,geni-spi";
1716 clock-names = "se";
1717 pinctrl-names = "default";
1718 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1720 #address-cells = <1>;
1721 #size-cells = <0>;
1722 power-domains = <&rpmhpd SC7280_CX>;
1723 operating-points-v2 = <&qup_opp_table>;
1726 interconnect-names = "qup-core", "qup-config";
1729 dma-names = "tx", "rx";
1734 compatible = "qcom,geni-uart";
1737 clock-names = "se";
1738 pinctrl-names = "default";
1739 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1741 power-domains = <&rpmhpd SC7280_CX>;
1742 operating-points-v2 = <&qup_opp_table>;
1745 interconnect-names = "qup-core", "qup-config";
1750 compatible = "qcom,geni-i2c";
1753 clock-names = "se";
1754 pinctrl-names = "default";
1755 pinctrl-0 = <&qup_i2c12_data_clk>;
1757 #address-cells = <1>;
1758 #size-cells = <0>;
1762 interconnect-names = "qup-core", "qup-config",
1763 "qup-memory";
1764 power-domains = <&rpmhpd SC7280_CX>;
1765 required-opps = <&rpmhpd_opp_low_svs>;
1768 dma-names = "tx", "rx";
1773 compatible = "qcom,geni-spi";
1776 clock-names = "se";
1777 pinctrl-names = "default";
1778 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1780 #address-cells = <1>;
1781 #size-cells = <0>;
1782 power-domains = <&rpmhpd SC7280_CX>;
1783 operating-points-v2 = <&qup_opp_table>;
1786 interconnect-names = "qup-core", "qup-config";
1789 dma-names = "tx", "rx";
1794 compatible = "qcom,geni-uart";
1797 clock-names = "se";
1798 pinctrl-names = "default";
1799 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1801 power-domains = <&rpmhpd SC7280_CX>;
1802 operating-points-v2 = <&qup_opp_table>;
1805 interconnect-names = "qup-core", "qup-config";
1810 compatible = "qcom,geni-i2c";
1813 clock-names = "se";
1814 pinctrl-names = "default";
1815 pinctrl-0 = <&qup_i2c13_data_clk>;
1817 #address-cells = <1>;
1818 #size-cells = <0>;
1822 interconnect-names = "qup-core", "qup-config",
1823 "qup-memory";
1824 power-domains = <&rpmhpd SC7280_CX>;
1825 required-opps = <&rpmhpd_opp_low_svs>;
1828 dma-names = "tx", "rx";
1833 compatible = "qcom,geni-spi";
1836 clock-names = "se";
1837 pinctrl-names = "default";
1838 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1840 #address-cells = <1>;
1841 #size-cells = <0>;
1842 power-domains = <&rpmhpd SC7280_CX>;
1843 operating-points-v2 = <&qup_opp_table>;
1846 interconnect-names = "qup-core", "qup-config";
1849 dma-names = "tx", "rx";
1854 compatible = "qcom,geni-uart";
1857 clock-names = "se";
1858 pinctrl-names = "default";
1859 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1861 power-domains = <&rpmhpd SC7280_CX>;
1862 operating-points-v2 = <&qup_opp_table>;
1865 interconnect-names = "qup-core", "qup-config";
1870 compatible = "qcom,geni-i2c";
1873 clock-names = "se";
1874 pinctrl-names = "default";
1875 pinctrl-0 = <&qup_i2c14_data_clk>;
1877 #address-cells = <1>;
1878 #size-cells = <0>;
1882 interconnect-names = "qup-core", "qup-config",
1883 "qup-memory";
1884 power-domains = <&rpmhpd SC7280_CX>;
1885 required-opps = <&rpmhpd_opp_low_svs>;
1888 dma-names = "tx", "rx";
1893 compatible = "qcom,geni-spi";
1896 clock-names = "se";
1897 pinctrl-names = "default";
1898 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1900 #address-cells = <1>;
1901 #size-cells = <0>;
1902 power-domains = <&rpmhpd SC7280_CX>;
1903 operating-points-v2 = <&qup_opp_table>;
1906 interconnect-names = "qup-core", "qup-config";
1909 dma-names = "tx", "rx";
1914 compatible = "qcom,geni-uart";
1917 clock-names = "se";
1918 pinctrl-names = "default";
1919 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
1921 power-domains = <&rpmhpd SC7280_CX>;
1922 operating-points-v2 = <&qup_opp_table>;
1925 interconnect-names = "qup-core", "qup-config";
1930 compatible = "qcom,geni-i2c";
1933 clock-names = "se";
1934 pinctrl-names = "default";
1935 pinctrl-0 = <&qup_i2c15_data_clk>;
1937 #address-cells = <1>;
1938 #size-cells = <0>;
1942 interconnect-names = "qup-core", "qup-config",
1943 "qup-memory";
1944 power-domains = <&rpmhpd SC7280_CX>;
1945 required-opps = <&rpmhpd_opp_low_svs>;
1948 dma-names = "tx", "rx";
1953 compatible = "qcom,geni-spi";
1956 clock-names = "se";
1957 pinctrl-names = "default";
1958 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1960 #address-cells = <1>;
1961 #size-cells = <0>;
1962 power-domains = <&rpmhpd SC7280_CX>;
1963 operating-points-v2 = <&qup_opp_table>;
1966 interconnect-names = "qup-core", "qup-config";
1969 dma-names = "tx", "rx";
1974 compatible = "qcom,geni-uart";
1977 clock-names = "se";
1978 pinctrl-names = "default";
1979 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
1981 power-domains = <&rpmhpd SC7280_CX>;
1982 operating-points-v2 = <&qup_opp_table>;
1985 interconnect-names = "qup-core", "qup-config";
1992 compatible = "qcom,sc7280-cnoc2";
1993 #interconnect-cells = <2>;
1994 qcom,bcm-voters = <&apps_bcm_voter>;
1999 compatible = "qcom,sc7280-cnoc3";
2000 #interconnect-cells = <2>;
2001 qcom,bcm-voters = <&apps_bcm_voter>;
2006 compatible = "qcom,sc7280-mc-virt";
2007 #interconnect-cells = <2>;
2008 qcom,bcm-voters = <&apps_bcm_voter>;
2013 compatible = "qcom,sc7280-system-noc";
2014 #interconnect-cells = <2>;
2015 qcom,bcm-voters = <&apps_bcm_voter>;
2019 compatible = "qcom,sc7280-aggre1-noc";
2021 #interconnect-cells = <2>;
2022 qcom,bcm-voters = <&apps_bcm_voter>;
2027 compatible = "qcom,sc7280-aggre2-noc";
2028 #interconnect-cells = <2>;
2029 qcom,bcm-voters = <&apps_bcm_voter>;
2034 compatible = "qcom,sc7280-mmss-noc";
2035 #interconnect-cells = <2>;
2036 qcom,bcm-voters = <&apps_bcm_voter>;
2040 compatible = "qcom,wcn6750-wifi";
2076 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>;
2078 qcom,smem-states = <&wlan_smp2p_out 0>;
2079 qcom,smem-state-names = "wlan-smp2p-out";
2083 compatible = "qcom,pcie-sc7280";
2090 reg-names = "parf", "dbi", "elbi", "atu", "config";
2092 linux,pci-domain = <1>;
2093 bus-range = <0x00 0xff>;
2094 num-lanes = <2>;
2096 #address-cells = <3>;
2097 #size-cells = <2>;
2110 interrupt-names = "msi0", "msi1", "msi2", "msi3",
2112 #interrupt-cells = <1>;
2113 interrupt-map-mask = <0 0 0 0x7>;
2114 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2133 clock-names = "pipe",
2147 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2148 assigned-clock-rates = <19200000>;
2151 reset-names = "pci";
2153 power-domains = <&gcc GCC_PCIE_1_GDSC>;
2156 phy-names = "pciephy";
2158 pinctrl-names = "default";
2159 pinctrl-0 = <&pcie1_clkreq_n>;
2161 dma-coherent;
2163 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2170 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
2172 #address-cells = <2>;
2173 #size-cells = <2>;
2179 clock-names = "aux", "cfg_ahb", "ref", "refgen";
2182 reset-names = "phy";
2184 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
2185 assigned-clock-rates = <100000000>;
2197 clock-names = "pipe0";
2199 #phy-cells = <0>;
2200 #clock-cells = <0>;
2201 clock-output-names = "pcie_1_pipe_clk";
2206 compatible = "qcom,sc7280-ipa";
2213 reg-names = "ipa-reg",
2214 "ipa-shared",
2217 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>,
2221 interrupt-names = "ipa",
2223 "ipa-clock-query",
2224 "ipa-setup-ready";
2227 clock-names = "core";
2231 interconnect-names = "memory",
2236 qcom,smem-states = <&ipa_smp2p_out 0>,
2238 qcom,smem-state-names = "ipa-clock-enabled-valid",
2239 "ipa-clock-enabled";
2245 compatible = "qcom,tcsr-mutex";
2247 #hwlock-cells = <1>;
2251 compatible = "qcom,sc7280-tcsr", "syscon";
2256 compatible = "qcom,sc7280-tcsr", "syscon";
2261 compatible = "qcom,sc7280-lpasscc";
2264 reg-names = "qdsp6ss", "top_cc";
2266 clock-names = "iface";
2267 #clock-cells = <1>;
2272 compatible = "qcom,sc7280-lpass-rx-macro";
2275 pinctrl-names = "default";
2276 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2281 clock-names = "mclk", "npl", "fsgen";
2283 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2285 power-domain-names = "macro", "dcodec";
2287 #clock-cells = <0>;
2288 #sound-dai-cells = <1>;
2294 compatible = "qcom,soundwire-v1.6.0";
2299 clock-names = "iface";
2301 qcom,din-ports = <0>;
2302 qcom,dout-ports = <5>;
2305 reset-names = "swr_audio_cgcr";
2307 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2308 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2309 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2310 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2311 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2312 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2313 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2314 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2315 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2317 #sound-dai-cells = <1>;
2318 #address-cells = <2>;
2319 #size-cells = <0>;
2325 compatible = "qcom,sc7280-lpass-tx-macro";
2328 pinctrl-names = "default";
2329 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2334 clock-names = "mclk", "npl", "fsgen";
2336 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2338 power-domain-names = "macro", "dcodec";
2340 #clock-cells = <0>;
2341 #sound-dai-cells = <1>;
2347 compatible = "qcom,soundwire-v1.6.0";
2350 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
2353 clock-names = "iface";
2355 qcom,din-ports = <3>;
2356 qcom,dout-ports = <0>;
2359 reset-names = "swr_audio_cgcr";
2361 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2362 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2363 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2364 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2365 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2366 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2367 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2368 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2369 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2371 #sound-dai-cells = <1>;
2372 #address-cells = <2>;
2373 #size-cells = <0>;
2378 lpass_audiocc: clock-controller@3300000 {
2379 compatible = "qcom,sc7280-lpassaudiocc";
2384 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src";
2385 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>;
2386 #clock-cells = <1>;
2387 #power-domain-cells = <1>;
2388 #reset-cells = <1>;
2392 compatible = "qcom,sc7280-lpass-va-macro";
2395 pinctrl-names = "default";
2396 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2399 clock-names = "mclk";
2401 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>,
2403 power-domain-names = "macro", "dcodec";
2405 #clock-cells = <0>;
2406 #sound-dai-cells = <1>;
2411 lpass_aon: clock-controller@3380000 {
2412 compatible = "qcom,sc7280-lpassaoncc";
2417 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface";
2418 #clock-cells = <1>;
2419 #power-domain-cells = <1>;
2423 lpass_core: clock-controller@3900000 {
2424 compatible = "qcom,sc7280-lpasscorecc";
2427 clock-names = "bi_tcxo";
2428 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>;
2429 #clock-cells = <1>;
2430 #power-domain-cells = <1>;
2435 compatible = "qcom,sc7280-lpass-cpu";
2443 reg-names = "lpass-hdmiif",
2444 "lpass-lpaif",
2445 "lpass-rxtx-cdc-dma-lpm",
2446 "lpass-rxtx-lpaif",
2447 "lpass-va-lpaif",
2448 "lpass-va-cdc-dma-lpm";
2454 power-domains = <&rpmhpd SC7280_LCX>;
2455 power-domain-names = "lcx";
2456 required-opps = <&rpmhpd_opp_nom>;
2468 clock-names = "aon_cc_audio_hm_h",
2479 #sound-dai-cells = <1>;
2480 #address-cells = <1>;
2481 #size-cells = <0>;
2487 interrupt-names = "lpass-irq-lpaif",
2488 "lpass-irq-hdmi",
2489 "lpass-irq-vaif",
2490 "lpass-irq-rxtxif";
2495 lpass_hm: clock-controller@3c00000 {
2496 compatible = "qcom,sc7280-lpasshm";
2499 clock-names = "bi_tcxo";
2500 #clock-cells = <1>;
2501 #power-domain-cells = <1>;
2507 compatible = "qcom,sc7280-lpass-ag-noc";
2508 #interconnect-cells = <2>;
2509 qcom,bcm-voters = <&apps_bcm_voter>;
2513 compatible = "qcom,sc7280-lpass-lpi-pinctrl";
2516 qcom,adsp-bypass-mode;
2517 gpio-controller;
2518 #gpio-cells = <2>;
2519 gpio-ranges = <&lpass_tlmm 0 0 15>;
2521 lpass_dmic01_clk: dmic01-clk-state {
2526 lpass_dmic01_data: dmic01-data-state {
2531 lpass_dmic23_clk: dmic23-clk-state {
2536 lpass_dmic23_data: dmic23-data-state {
2541 lpass_rx_swr_clk: rx-swr-clk-state {
2546 lpass_rx_swr_data: rx-swr-data-state {
2551 lpass_tx_swr_clk: tx-swr-clk-state {
2556 lpass_tx_swr_data: tx-swr-data-state {
2563 compatible = "qcom,adreno-635.0", "qcom,adreno";
2567 reg-names = "kgsl_3d0_reg_memory",
2573 operating-points-v2 = <&gpu_opp_table>;
2576 interconnect-names = "gfx-mem";
2577 #cooling-cells = <2>;
2579 nvmem-cells = <&gpu_speed_bin>;
2580 nvmem-cell-names = "speed_bin";
2582 gpu_opp_table: opp-table {
2583 compatible = "operating-points-v2";
2585 opp-315000000 {
2586 opp-hz = /bits/ 64 <315000000>;
2587 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2588 opp-peak-kBps = <1804000>;
2589 opp-supported-hw = <0x03>;
2592 opp-450000000 {
2593 opp-hz = /bits/ 64 <450000000>;
2594 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2595 opp-peak-kBps = <4068000>;
2596 opp-supported-hw = <0x03>;
2600 opp-550000000-0 {
2601 opp-hz = /bits/ 64 <550000000>;
2602 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2603 opp-peak-kBps = <8368000>;
2604 opp-supported-hw = <0x01>;
2607 opp-550000000-1 {
2608 opp-hz = /bits/ 64 <550000000>;
2609 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2610 opp-peak-kBps = <6832000>;
2611 opp-supported-hw = <0x02>;
2614 opp-608000000 {
2615 opp-hz = /bits/ 64 <608000000>;
2616 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
2617 opp-peak-kBps = <8368000>;
2618 opp-supported-hw = <0x02>;
2621 opp-700000000 {
2622 opp-hz = /bits/ 64 <700000000>;
2623 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2624 opp-peak-kBps = <8532000>;
2625 opp-supported-hw = <0x02>;
2628 opp-812000000 {
2629 opp-hz = /bits/ 64 <812000000>;
2630 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2631 opp-peak-kBps = <8532000>;
2632 opp-supported-hw = <0x02>;
2635 opp-840000000 {
2636 opp-hz = /bits/ 64 <840000000>;
2637 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2638 opp-peak-kBps = <8532000>;
2639 opp-supported-hw = <0x02>;
2642 opp-900000000 {
2643 opp-hz = /bits/ 64 <900000000>;
2644 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2645 opp-peak-kBps = <8532000>;
2646 opp-supported-hw = <0x02>;
2652 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
2656 reg-names = "gmu", "rscc", "gmu_pdc";
2659 interrupt-names = "hfi", "gmu";
2667 clock-names = "gmu",
2674 power-domains = <&gpucc GPU_CC_CX_GDSC>,
2676 power-domain-names = "cx",
2679 operating-points-v2 = <&gmu_opp_table>;
2681 gmu_opp_table: opp-table {
2682 compatible = "operating-points-v2";
2684 opp-200000000 {
2685 opp-hz = /bits/ 64 <200000000>;
2686 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2691 gpucc: clock-controller@3d90000 {
2692 compatible = "qcom,sc7280-gpucc";
2697 clock-names = "bi_tcxo",
2700 #clock-cells = <1>;
2701 #reset-cells = <1>;
2702 #power-domain-cells = <1>;
2706 compatible = "qcom,sc7280-dcc", "qcom,dcc";
2712 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu",
2713 "qcom,smmu-500", "arm,mmu-500";
2715 #iommu-cells = <2>;
2716 #global-interrupts = <2>;
2737 clock-names = "gcc_gpu_memnoc_gfx_clk",
2745 power-domains = <&gpucc GPU_CC_CX_GDSC>;
2746 dma-coherent;
2750 compatible = "qcom,sc7280-mpss-pas";
2752 reg-names = "qdsp6", "rmb";
2754 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
2760 interrupt-names = "wdog", "fatal", "ready", "handover",
2761 "stop-ack", "shutdown-ack";
2764 clock-names = "xo";
2766 power-domains = <&rpmhpd SC7280_CX>,
2768 power-domain-names = "cx", "mss";
2770 memory-region = <&mpss_mem>;
2774 qcom,smem-states = <&modem_smp2p_out 0>;
2775 qcom,smem-state-names = "stop";
2779 glink-edge {
2780 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
2786 qcom,remote-pid = <1>;
2791 compatible = "arm,coresight-stm", "arm,primecell";
2794 reg-names = "stm-base", "stm-stimulus-base";
2797 clock-names = "apb_pclk";
2799 out-ports {
2802 remote-endpoint = <&funnel0_in7>;
2809 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2813 clock-names = "apb_pclk";
2815 out-ports {
2818 remote-endpoint = <&merge_funnel_in0>;
2823 in-ports {
2824 #address-cells = <1>;
2825 #size-cells = <0>;
2830 remote-endpoint = <&stm_out>;
2837 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2841 clock-names = "apb_pclk";
2843 out-ports {
2846 remote-endpoint = <&merge_funnel_in1>;
2851 in-ports {
2852 #address-cells = <1>;
2853 #size-cells = <0>;
2858 remote-endpoint = <&apss_merge_funnel_out>;
2865 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2869 clock-names = "apb_pclk";
2871 out-ports {
2874 remote-endpoint = <&swao_funnel_in>;
2879 in-ports {
2880 #address-cells = <1>;
2881 #size-cells = <0>;
2886 remote-endpoint = <&funnel0_out>;
2893 remote-endpoint = <&funnel1_out>;
2900 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2904 clock-names = "apb_pclk";
2906 out-ports {
2909 remote-endpoint = <&etr_in>;
2914 in-ports {
2917 remote-endpoint = <&swao_replicator_out>;
2924 compatible = "arm,coresight-tmc", "arm,primecell";
2929 clock-names = "apb_pclk";
2930 arm,scatter-gather;
2932 in-ports {
2935 remote-endpoint = <&replicator_out>;
2942 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2946 clock-names = "apb_pclk";
2948 out-ports {
2951 remote-endpoint = <&etf_in>;
2956 in-ports {
2957 #address-cells = <1>;
2958 #size-cells = <0>;
2963 remote-endpoint = <&merge_funnel_out>;
2970 compatible = "arm,coresight-tmc", "arm,primecell";
2974 clock-names = "apb_pclk";
2976 out-ports {
2979 remote-endpoint = <&swao_replicator_in>;
2984 in-ports {
2987 remote-endpoint = <&swao_funnel_out>;
2994 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2998 clock-names = "apb_pclk";
2999 qcom,replicator-loses-context;
3001 out-ports {
3004 remote-endpoint = <&replicator_in>;
3009 in-ports {
3012 remote-endpoint = <&etf_out>;
3019 compatible = "arm,coresight-etm4x", "arm,primecell";
3025 clock-names = "apb_pclk";
3026 arm,coresight-loses-context-with-cpu;
3027 qcom,skip-power-up;
3029 out-ports {
3032 remote-endpoint = <&apss_funnel_in0>;
3039 compatible = "arm,coresight-etm4x", "arm,primecell";
3045 clock-names = "apb_pclk";
3046 arm,coresight-loses-context-with-cpu;
3047 qcom,skip-power-up;
3049 out-ports {
3052 remote-endpoint = <&apss_funnel_in1>;
3059 compatible = "arm,coresight-etm4x", "arm,primecell";
3065 clock-names = "apb_pclk";
3066 arm,coresight-loses-context-with-cpu;
3067 qcom,skip-power-up;
3069 out-ports {
3072 remote-endpoint = <&apss_funnel_in2>;
3079 compatible = "arm,coresight-etm4x", "arm,primecell";
3085 clock-names = "apb_pclk";
3086 arm,coresight-loses-context-with-cpu;
3087 qcom,skip-power-up;
3089 out-ports {
3092 remote-endpoint = <&apss_funnel_in3>;
3099 compatible = "arm,coresight-etm4x", "arm,primecell";
3105 clock-names = "apb_pclk";
3106 arm,coresight-loses-context-with-cpu;
3107 qcom,skip-power-up;
3109 out-ports {
3112 remote-endpoint = <&apss_funnel_in4>;
3119 compatible = "arm,coresight-etm4x", "arm,primecell";
3125 clock-names = "apb_pclk";
3126 arm,coresight-loses-context-with-cpu;
3127 qcom,skip-power-up;
3129 out-ports {
3132 remote-endpoint = <&apss_funnel_in5>;
3139 compatible = "arm,coresight-etm4x", "arm,primecell";
3145 clock-names = "apb_pclk";
3146 arm,coresight-loses-context-with-cpu;
3147 qcom,skip-power-up;
3149 out-ports {
3152 remote-endpoint = <&apss_funnel_in6>;
3159 compatible = "arm,coresight-etm4x", "arm,primecell";
3165 clock-names = "apb_pclk";
3166 arm,coresight-loses-context-with-cpu;
3167 qcom,skip-power-up;
3169 out-ports {
3172 remote-endpoint = <&apss_funnel_in7>;
3179 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3183 clock-names = "apb_pclk";
3185 out-ports {
3188 remote-endpoint = <&apss_merge_funnel_in>;
3193 in-ports {
3194 #address-cells = <1>;
3195 #size-cells = <0>;
3200 remote-endpoint = <&etm0_out>;
3207 remote-endpoint = <&etm1_out>;
3214 remote-endpoint = <&etm2_out>;
3221 remote-endpoint = <&etm3_out>;
3228 remote-endpoint = <&etm4_out>;
3235 remote-endpoint = <&etm5_out>;
3242 remote-endpoint = <&etm6_out>;
3249 remote-endpoint = <&etm7_out>;
3256 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
3260 clock-names = "apb_pclk";
3262 out-ports {
3265 remote-endpoint = <&funnel1_in4>;
3270 in-ports {
3273 remote-endpoint = <&apss_funnel_out>;
3280 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
3281 pinctrl-names = "default", "sleep";
3282 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3283 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
3291 interrupt-names = "hc_irq", "pwr_irq";
3296 clock-names = "iface", "core", "xo";
3299 interconnect-names = "sdhc-ddr","cpu-sdhc";
3300 power-domains = <&rpmhpd SC7280_CX>;
3301 operating-points-v2 = <&sdhc2_opp_table>;
3303 bus-width = <4>;
3304 dma-coherent;
3306 qcom,dll-config = <0x0007642c>;
3310 sdhc2_opp_table: opp-table {
3311 compatible = "operating-points-v2";
3313 opp-100000000 {
3314 opp-hz = /bits/ 64 <100000000>;
3315 required-opps = <&rpmhpd_opp_low_svs>;
3316 opp-peak-kBps = <1800000 400000>;
3317 opp-avg-kBps = <100000 0>;
3320 opp-202000000 {
3321 opp-hz = /bits/ 64 <202000000>;
3322 required-opps = <&rpmhpd_opp_nom>;
3323 opp-peak-kBps = <5400000 1600000>;
3324 opp-avg-kBps = <200000 0>;
3330 compatible = "qcom,sc7280-usb-hs-phy",
3331 "qcom,usb-snps-hs-7nm-phy";
3334 #phy-cells = <0>;
3337 clock-names = "ref";
3343 compatible = "qcom,sc7280-usb-hs-phy",
3344 "qcom,usb-snps-hs-7nm-phy";
3347 #phy-cells = <0>;
3350 clock-names = "ref";
3356 compatible = "qcom,sc7280-qmp-usb3-dp-phy";
3364 clock-names = "aux",
3371 reset-names = "phy", "common";
3373 #clock-cells = <1>;
3374 #phy-cells = <1>;
3378 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3381 #address-cells = <2>;
3382 #size-cells = <2>;
3384 dma-ranges;
3391 clock-names = "cfg_noc",
3397 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
3399 assigned-clock-rates = <19200000>, <200000000>;
3401 interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
3404 interrupt-names = "hs_phy_irq",
3408 power-domains = <&gcc GCC_USB30_SEC_GDSC>;
3409 required-opps = <&rpmhpd_opp_nom>;
3415 interconnect-names = "usb-ddr", "apps-usb";
3425 phy-names = "usb2-phy";
3426 maximum-speed = "high-speed";
3427 usb-role-switch;
3431 remote-endpoint = <&eud_ep>;
3438 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
3441 #address-cells = <1>;
3442 #size-cells = <0>;
3446 clock-names = "iface", "core";
3449 interconnect-names = "qspi-config";
3450 power-domains = <&rpmhpd SC7280_CX>;
3451 operating-points-v2 = <&qspi_opp_table>;
3456 compatible = "qcom,sc7280-wpss-pil";
3459 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
3465 interrupt-names = "wdog", "fatal", "ready", "handover",
3466 "stop-ack", "shutdown-ack";
3472 clock-names = "ahb_bdg", "ahb",
3475 power-domains = <&rpmhpd SC7280_CX>,
3477 power-domain-names = "cx", "mx";
3479 memory-region = <&wpss_mem>;
3483 qcom,smem-states = <&wpss_smp2p_out 0>;
3484 qcom,smem-state-names = "stop";
3488 reset-names = "restart", "pdc_sync";
3490 qcom,halt-regs = <&tcsr_1 0x17000>;
3494 glink-edge {
3495 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
3502 qcom,remote-pid = <13>;
3507 compatible = "qcom,sc7280-llcc-bwmon";
3514 operating-points-v2 = <&llcc_bwmon_opp_table>;
3516 llcc_bwmon_opp_table: opp-table {
3517 compatible = "operating-points-v2";
3519 opp-0 {
3520 opp-peak-kBps = <800000>;
3522 opp-1 {
3523 opp-peak-kBps = <1804000>;
3525 opp-2 {
3526 opp-peak-kBps = <2188000>;
3528 opp-3 {
3529 opp-peak-kBps = <3072000>;
3531 opp-4 {
3532 opp-peak-kBps = <4068000>;
3534 opp-5 {
3535 opp-peak-kBps = <6220000>;
3537 opp-6 {
3538 opp-peak-kBps = <6832000>;
3540 opp-7 {
3541 opp-peak-kBps = <8532000>;
3547 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon";
3553 operating-points-v2 = <&cpu_bwmon_opp_table>;
3555 cpu_bwmon_opp_table: opp-table {
3556 compatible = "operating-points-v2";
3558 opp-0 {
3559 opp-peak-kBps = <2400000>;
3561 opp-1 {
3562 opp-peak-kBps = <4800000>;
3564 opp-2 {
3565 opp-peak-kBps = <7456000>;
3567 opp-3 {
3568 opp-peak-kBps = <9600000>;
3570 opp-4 {
3571 opp-peak-kBps = <12896000>;
3573 opp-5 {
3574 opp-peak-kBps = <14928000>;
3576 opp-6 {
3577 opp-peak-kBps = <17056000>;
3584 compatible = "qcom,sc7280-dc-noc";
3585 #interconnect-cells = <2>;
3586 qcom,bcm-voters = <&apps_bcm_voter>;
3591 compatible = "qcom,sc7280-gem-noc";
3592 #interconnect-cells = <2>;
3593 qcom,bcm-voters = <&apps_bcm_voter>;
3596 system-cache-controller@9200000 {
3597 compatible = "qcom,sc7280-llcc";
3600 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base";
3605 compatible = "qcom,sc7280-eud", "qcom,eud";
3608 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>;
3613 #address-cells = <1>;
3614 #size-cells = <0>;
3619 remote-endpoint = <&usb2_role_switch>;
3627 compatible = "qcom,sc7280-nsp-noc";
3628 #interconnect-cells = <2>;
3629 qcom,bcm-voters = <&apps_bcm_voter>;
3633 compatible = "qcom,sc7280-dwc3", "qcom,dwc3";
3636 #address-cells = <2>;
3637 #size-cells = <2>;
3639 dma-ranges;
3646 clock-names = "cfg_noc",
3652 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
3654 assigned-clock-rates = <19200000>, <200000000>;
3656 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
3660 interrupt-names = "hs_phy_irq",
3665 power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
3666 required-opps = <&rpmhpd_opp_nom>;
3672 interconnect-names = "usb-ddr", "apps-usb";
3674 wakeup-source;
3683 snps,parkmode-disable-ss-quirk;
3685 phy-names = "usb2-phy", "usb3-phy";
3686 maximum-speed = "super-speed";
3690 venus: video-codec@aa00000 {
3691 compatible = "qcom,sc7280-venus";
3700 clock-names = "core", "bus", "iface",
3703 power-domains = <&videocc MVSC_GDSC>,
3706 power-domain-names = "venus", "vcodec0", "cx";
3707 operating-points-v2 = <&venus_opp_table>;
3711 interconnect-names = "cpu-cfg", "video-mem";
3715 memory-region = <&video_mem>;
3717 video-decoder {
3718 compatible = "venus-decoder";
3721 video-encoder {
3722 compatible = "venus-encoder";
3725 video-firmware {
3729 venus_opp_table: opp-table {
3730 compatible = "operating-points-v2";
3732 opp-133330000 {
3733 opp-hz = /bits/ 64 <133330000>;
3734 required-opps = <&rpmhpd_opp_low_svs>;
3737 opp-240000000 {
3738 opp-hz = /bits/ 64 <240000000>;
3739 required-opps = <&rpmhpd_opp_svs>;
3742 opp-335000000 {
3743 opp-hz = /bits/ 64 <335000000>;
3744 required-opps = <&rpmhpd_opp_svs_l1>;
3747 opp-424000000 {
3748 opp-hz = /bits/ 64 <424000000>;
3749 required-opps = <&rpmhpd_opp_nom>;
3752 opp-460000048 {
3753 opp-hz = /bits/ 64 <460000048>;
3754 required-opps = <&rpmhpd_opp_turbo>;
3759 videocc: clock-controller@aaf0000 {
3760 compatible = "qcom,sc7280-videocc";
3764 clock-names = "bi_tcxo", "bi_tcxo_ao";
3765 #clock-cells = <1>;
3766 #reset-cells = <1>;
3767 #power-domain-cells = <1>;
3770 camcc: clock-controller@ad00000 {
3771 compatible = "qcom,sc7280-camcc";
3776 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
3777 #clock-cells = <1>;
3778 #reset-cells = <1>;
3779 #power-domain-cells = <1>;
3782 dispcc: clock-controller@af00000 {
3783 compatible = "qcom,sc7280-dispcc";
3793 clock-names = "bi_tcxo",
3801 #clock-cells = <1>;
3802 #reset-cells = <1>;
3803 #power-domain-cells = <1>;
3806 mdss: display-subsystem@ae00000 {
3807 compatible = "qcom,sc7280-mdss";
3809 reg-names = "mdss";
3811 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
3816 clock-names = "iface",
3821 interrupt-controller;
3822 #interrupt-cells = <1>;
3825 interconnect-names = "mdp0-mem";
3829 #address-cells = <2>;
3830 #size-cells = <2>;
3835 mdss_mdp: display-controller@ae01000 {
3836 compatible = "qcom,sc7280-dpu";
3839 reg-names = "mdp", "vbif";
3847 clock-names = "bus",
3853 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3855 assigned-clock-rates = <19200000>,
3857 operating-points-v2 = <&mdp_opp_table>;
3858 power-domains = <&rpmhpd SC7280_CX>;
3860 interrupt-parent = <&mdss>;
3864 #address-cells = <1>;
3865 #size-cells = <0>;
3870 remote-endpoint = <&mdss_dsi0_in>;
3877 remote-endpoint = <&edp_in>;
3884 remote-endpoint = <&dp_in>;
3889 mdp_opp_table: opp-table {
3890 compatible = "operating-points-v2";
3892 opp-200000000 {
3893 opp-hz = /bits/ 64 <200000000>;
3894 required-opps = <&rpmhpd_opp_low_svs>;
3897 opp-300000000 {
3898 opp-hz = /bits/ 64 <300000000>;
3899 required-opps = <&rpmhpd_opp_svs>;
3902 opp-380000000 {
3903 opp-hz = /bits/ 64 <380000000>;
3904 required-opps = <&rpmhpd_opp_svs_l1>;
3907 opp-506666667 {
3908 opp-hz = /bits/ 64 <506666667>;
3909 required-opps = <&rpmhpd_opp_nom>;
3915 compatible = "qcom,sc7280-dsi-ctrl",
3916 "qcom,mdss-dsi-ctrl";
3918 reg-names = "dsi_ctrl";
3920 interrupt-parent = <&mdss>;
3929 clock-names = "byte",
3936 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3937 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
3939 operating-points-v2 = <&dsi_opp_table>;
3940 power-domains = <&rpmhpd SC7280_CX>;
3944 #address-cells = <1>;
3945 #size-cells = <0>;
3950 #address-cells = <1>;
3951 #size-cells = <0>;
3956 remote-endpoint = <&dpu_intf1_out>;
3967 dsi_opp_table: opp-table {
3968 compatible = "operating-points-v2";
3970 opp-187500000 {
3971 opp-hz = /bits/ 64 <187500000>;
3972 required-opps = <&rpmhpd_opp_low_svs>;
3975 opp-300000000 {
3976 opp-hz = /bits/ 64 <300000000>;
3977 required-opps = <&rpmhpd_opp_svs>;
3980 opp-358000000 {
3981 opp-hz = /bits/ 64 <358000000>;
3982 required-opps = <&rpmhpd_opp_svs_l1>;
3988 compatible = "qcom,sc7280-dsi-phy-7nm";
3992 reg-names = "dsi_phy",
3996 #clock-cells = <1>;
3997 #phy-cells = <0>;
4001 clock-names = "iface", "ref";
4007 compatible = "qcom,sc7280-edp";
4008 pinctrl-names = "default";
4009 pinctrl-0 = <&edp_hot_plug_det>;
4016 interrupt-parent = <&mdss>;
4024 clock-names = "core_iface",
4029 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
4031 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4034 phy-names = "dp";
4036 operating-points-v2 = <&edp_opp_table>;
4037 power-domains = <&rpmhpd SC7280_CX>;
4042 #address-cells = <1>;
4043 #size-cells = <0>;
4048 remote-endpoint = <&dpu_intf5_out>;
4058 edp_opp_table: opp-table {
4059 compatible = "operating-points-v2";
4061 opp-160000000 {
4062 opp-hz = /bits/ 64 <160000000>;
4063 required-opps = <&rpmhpd_opp_low_svs>;
4066 opp-270000000 {
4067 opp-hz = /bits/ 64 <270000000>;
4068 required-opps = <&rpmhpd_opp_svs>;
4071 opp-540000000 {
4072 opp-hz = /bits/ 64 <540000000>;
4073 required-opps = <&rpmhpd_opp_nom>;
4076 opp-810000000 {
4077 opp-hz = /bits/ 64 <810000000>;
4078 required-opps = <&rpmhpd_opp_nom>;
4084 compatible = "qcom,sc7280-edp-phy";
4093 clock-names = "aux",
4096 #clock-cells = <1>;
4097 #phy-cells = <0>;
4102 mdss_dp: displayport-controller@ae90000 {
4103 compatible = "qcom,sc7280-dp";
4111 interrupt-parent = <&mdss>;
4119 clock-names = "core_iface",
4124 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
4126 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
4129 phy-names = "dp";
4131 operating-points-v2 = <&dp_opp_table>;
4132 power-domains = <&rpmhpd SC7280_CX>;
4134 #sound-dai-cells = <0>;
4139 #address-cells = <1>;
4140 #size-cells = <0>;
4145 remote-endpoint = <&dpu_intf0_out>;
4155 dp_opp_table: opp-table {
4156 compatible = "operating-points-v2";
4158 opp-160000000 {
4159 opp-hz = /bits/ 64 <160000000>;
4160 required-opps = <&rpmhpd_opp_low_svs>;
4163 opp-270000000 {
4164 opp-hz = /bits/ 64 <270000000>;
4165 required-opps = <&rpmhpd_opp_svs>;
4168 opp-540000000 {
4169 opp-hz = /bits/ 64 <540000000>;
4170 required-opps = <&rpmhpd_opp_svs_l1>;
4173 opp-810000000 {
4174 opp-hz = /bits/ 64 <810000000>;
4175 required-opps = <&rpmhpd_opp_nom>;
4181 pdc: interrupt-controller@b220000 {
4182 compatible = "qcom,sc7280-pdc", "qcom,pdc";
4184 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4189 #interrupt-cells = <2>;
4190 interrupt-parent = <&intc>;
4191 interrupt-controller;
4194 pdc_reset: reset-controller@b5e0000 {
4195 compatible = "qcom,sc7280-pdc-global";
4197 #reset-cells = <1>;
4201 tsens0: thermal-sensor@c263000 {
4202 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4208 interrupt-names = "uplow","critical";
4209 #thermal-sensor-cells = <1>;
4212 tsens1: thermal-sensor@c265000 {
4213 compatible = "qcom,sc7280-tsens","qcom,tsens-v2";
4219 interrupt-names = "uplow","critical";
4220 #thermal-sensor-cells = <1>;
4223 aoss_reset: reset-controller@c2a0000 {
4224 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc";
4226 #reset-cells = <1>;
4229 aoss_qmp: power-management@c300000 {
4230 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp";
4232 interrupts-extended = <&ipcc IPCC_CLIENT_AOP
4238 #clock-cells = <0>;
4242 compatible = "qcom,rpmh-stats";
4247 compatible = "qcom,spmi-pmic-arb";
4253 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
4254 interrupt-names = "periph_irq";
4255 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
4258 #address-cells = <2>;
4259 #size-cells = <0>;
4260 interrupt-controller;
4261 #interrupt-cells = <4>;
4265 compatible = "qcom,sc7280-pinctrl";
4268 gpio-controller;
4269 #gpio-cells = <2>;
4270 interrupt-controller;
4271 #interrupt-cells = <2>;
4272 gpio-ranges = <&tlmm 0 0 175>;
4273 wakeup-parent = <&pdc>;
4275 dp_hot_plug_det: dp-hot-plug-det-state {
4280 edp_hot_plug_det: edp-hot-plug-det-state {
4285 mi2s0_data0: mi2s0-data0-state {
4290 mi2s0_data1: mi2s0-data1-state {
4295 mi2s0_mclk: mi2s0-mclk-state {
4300 mi2s0_sclk: mi2s0-sclk-state {
4305 mi2s0_ws: mi2s0-ws-state {
4310 mi2s1_data0: mi2s1-data0-state {
4315 mi2s1_sclk: mi2s1-sclk-state {
4320 mi2s1_ws: mi2s1-ws-state {
4325 pcie1_clkreq_n: pcie1-clkreq-n-state {
4330 qspi_clk: qspi-clk-state {
4335 qspi_cs0: qspi-cs0-state {
4340 qspi_cs1: qspi-cs1-state {
4345 qspi_data0: qspi-data0-state {
4350 qspi_data1: qspi-data1-state {
4355 qspi_data23: qspi-data23-state {
4360 qup_i2c0_data_clk: qup-i2c0-data-clk-state {
4365 qup_i2c1_data_clk: qup-i2c1-data-clk-state {
4370 qup_i2c2_data_clk: qup-i2c2-data-clk-state {
4375 qup_i2c3_data_clk: qup-i2c3-data-clk-state {
4380 qup_i2c4_data_clk: qup-i2c4-data-clk-state {
4385 qup_i2c5_data_clk: qup-i2c5-data-clk-state {
4390 qup_i2c6_data_clk: qup-i2c6-data-clk-state {
4395 qup_i2c7_data_clk: qup-i2c7-data-clk-state {
4400 qup_i2c8_data_clk: qup-i2c8-data-clk-state {
4405 qup_i2c9_data_clk: qup-i2c9-data-clk-state {
4410 qup_i2c10_data_clk: qup-i2c10-data-clk-state {
4415 qup_i2c11_data_clk: qup-i2c11-data-clk-state {
4420 qup_i2c12_data_clk: qup-i2c12-data-clk-state {
4425 qup_i2c13_data_clk: qup-i2c13-data-clk-state {
4430 qup_i2c14_data_clk: qup-i2c14-data-clk-state {
4435 qup_i2c15_data_clk: qup-i2c15-data-clk-state {
4440 qup_spi0_data_clk: qup-spi0-data-clk-state {
4445 qup_spi0_cs: qup-spi0-cs-state {
4450 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state {
4455 qup_spi1_data_clk: qup-spi1-data-clk-state {
4460 qup_spi1_cs: qup-spi1-cs-state {
4465 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state {
4470 qup_spi2_data_clk: qup-spi2-data-clk-state {
4475 qup_spi2_cs: qup-spi2-cs-state {
4480 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state {
4485 qup_spi3_data_clk: qup-spi3-data-clk-state {
4490 qup_spi3_cs: qup-spi3-cs-state {
4495 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state {
4500 qup_spi4_data_clk: qup-spi4-data-clk-state {
4505 qup_spi4_cs: qup-spi4-cs-state {
4510 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state {
4515 qup_spi5_data_clk: qup-spi5-data-clk-state {
4520 qup_spi5_cs: qup-spi5-cs-state {
4525 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state {
4530 qup_spi6_data_clk: qup-spi6-data-clk-state {
4535 qup_spi6_cs: qup-spi6-cs-state {
4540 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state {
4545 qup_spi7_data_clk: qup-spi7-data-clk-state {
4550 qup_spi7_cs: qup-spi7-cs-state {
4555 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state {
4560 qup_spi8_data_clk: qup-spi8-data-clk-state {
4565 qup_spi8_cs: qup-spi8-cs-state {
4570 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state {
4575 qup_spi9_data_clk: qup-spi9-data-clk-state {
4580 qup_spi9_cs: qup-spi9-cs-state {
4585 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state {
4590 qup_spi10_data_clk: qup-spi10-data-clk-state {
4595 qup_spi10_cs: qup-spi10-cs-state {
4600 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state {
4605 qup_spi11_data_clk: qup-spi11-data-clk-state {
4610 qup_spi11_cs: qup-spi11-cs-state {
4615 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state {
4620 qup_spi12_data_clk: qup-spi12-data-clk-state {
4625 qup_spi12_cs: qup-spi12-cs-state {
4630 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state {
4635 qup_spi13_data_clk: qup-spi13-data-clk-state {
4640 qup_spi13_cs: qup-spi13-cs-state {
4645 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state {
4650 qup_spi14_data_clk: qup-spi14-data-clk-state {
4655 qup_spi14_cs: qup-spi14-cs-state {
4660 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state {
4665 qup_spi15_data_clk: qup-spi15-data-clk-state {
4670 qup_spi15_cs: qup-spi15-cs-state {
4675 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state {
4680 qup_uart0_cts: qup-uart0-cts-state {
4685 qup_uart0_rts: qup-uart0-rts-state {
4690 qup_uart0_tx: qup-uart0-tx-state {
4695 qup_uart0_rx: qup-uart0-rx-state {
4700 qup_uart1_cts: qup-uart1-cts-state {
4705 qup_uart1_rts: qup-uart1-rts-state {
4710 qup_uart1_tx: qup-uart1-tx-state {
4715 qup_uart1_rx: qup-uart1-rx-state {
4720 qup_uart2_cts: qup-uart2-cts-state {
4725 qup_uart2_rts: qup-uart2-rts-state {
4730 qup_uart2_tx: qup-uart2-tx-state {
4735 qup_uart2_rx: qup-uart2-rx-state {
4740 qup_uart3_cts: qup-uart3-cts-state {
4745 qup_uart3_rts: qup-uart3-rts-state {
4750 qup_uart3_tx: qup-uart3-tx-state {
4755 qup_uart3_rx: qup-uart3-rx-state {
4760 qup_uart4_cts: qup-uart4-cts-state {
4765 qup_uart4_rts: qup-uart4-rts-state {
4770 qup_uart4_tx: qup-uart4-tx-state {
4775 qup_uart4_rx: qup-uart4-rx-state {
4780 qup_uart5_cts: qup-uart5-cts-state {
4785 qup_uart5_rts: qup-uart5-rts-state {
4790 qup_uart5_tx: qup-uart5-tx-state {
4795 qup_uart5_rx: qup-uart5-rx-state {
4800 qup_uart6_cts: qup-uart6-cts-state {
4805 qup_uart6_rts: qup-uart6-rts-state {
4810 qup_uart6_tx: qup-uart6-tx-state {
4815 qup_uart6_rx: qup-uart6-rx-state {
4820 qup_uart7_cts: qup-uart7-cts-state {
4825 qup_uart7_rts: qup-uart7-rts-state {
4830 qup_uart7_tx: qup-uart7-tx-state {
4835 qup_uart7_rx: qup-uart7-rx-state {
4840 qup_uart8_cts: qup-uart8-cts-state {
4845 qup_uart8_rts: qup-uart8-rts-state {
4850 qup_uart8_tx: qup-uart8-tx-state {
4855 qup_uart8_rx: qup-uart8-rx-state {
4860 qup_uart9_cts: qup-uart9-cts-state {
4865 qup_uart9_rts: qup-uart9-rts-state {
4870 qup_uart9_tx: qup-uart9-tx-state {
4875 qup_uart9_rx: qup-uart9-rx-state {
4880 qup_uart10_cts: qup-uart10-cts-state {
4885 qup_uart10_rts: qup-uart10-rts-state {
4890 qup_uart10_tx: qup-uart10-tx-state {
4895 qup_uart10_rx: qup-uart10-rx-state {
4900 qup_uart11_cts: qup-uart11-cts-state {
4905 qup_uart11_rts: qup-uart11-rts-state {
4910 qup_uart11_tx: qup-uart11-tx-state {
4915 qup_uart11_rx: qup-uart11-rx-state {
4920 qup_uart12_cts: qup-uart12-cts-state {
4925 qup_uart12_rts: qup-uart12-rts-state {
4930 qup_uart12_tx: qup-uart12-tx-state {
4935 qup_uart12_rx: qup-uart12-rx-state {
4940 qup_uart13_cts: qup-uart13-cts-state {
4945 qup_uart13_rts: qup-uart13-rts-state {
4950 qup_uart13_tx: qup-uart13-tx-state {
4955 qup_uart13_rx: qup-uart13-rx-state {
4960 qup_uart14_cts: qup-uart14-cts-state {
4965 qup_uart14_rts: qup-uart14-rts-state {
4970 qup_uart14_tx: qup-uart14-tx-state {
4975 qup_uart14_rx: qup-uart14-rx-state {
4980 qup_uart15_cts: qup-uart15-cts-state {
4985 qup_uart15_rts: qup-uart15-rts-state {
4990 qup_uart15_tx: qup-uart15-tx-state {
4995 qup_uart15_rx: qup-uart15-rx-state {
5000 sdc1_clk: sdc1-clk-state {
5004 sdc1_cmd: sdc1-cmd-state {
5008 sdc1_data: sdc1-data-state {
5012 sdc1_rclk: sdc1-rclk-state {
5016 sdc1_clk_sleep: sdc1-clk-sleep-state {
5018 drive-strength = <2>;
5019 bias-bus-hold;
5022 sdc1_cmd_sleep: sdc1-cmd-sleep-state {
5024 drive-strength = <2>;
5025 bias-bus-hold;
5028 sdc1_data_sleep: sdc1-data-sleep-state {
5030 drive-strength = <2>;
5031 bias-bus-hold;
5034 sdc1_rclk_sleep: sdc1-rclk-sleep-state {
5036 drive-strength = <2>;
5037 bias-bus-hold;
5040 sdc2_clk: sdc2-clk-state {
5044 sdc2_cmd: sdc2-cmd-state {
5048 sdc2_data: sdc2-data-state {
5052 sdc2_clk_sleep: sdc2-clk-sleep-state {
5054 drive-strength = <2>;
5055 bias-bus-hold;
5058 sdc2_cmd_sleep: sdc2-cmd-sleep-state {
5060 drive-strength = <2>;
5061 bias-bus-hold;
5064 sdc2_data_sleep: sdc2-data-sleep-state {
5066 drive-strength = <2>;
5067 bias-bus-hold;
5072 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd";
5075 #address-cells = <1>;
5076 #size-cells = <1>;
5080 pil-reloc@594c {
5081 compatible = "qcom,pil-reloc-info";
5087 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500";
5089 #iommu-cells = <2>;
5090 #global-interrupts = <1>;
5091 dma-coherent;
5175 intc: interrupt-controller@17a00000 {
5176 compatible = "arm,gic-v3";
5180 #interrupt-cells = <3>;
5181 interrupt-controller;
5182 #address-cells = <2>;
5183 #size-cells = <2>;
5186 msi-controller@17a40000 {
5187 compatible = "arm,gic-v3-its";
5189 msi-controller;
5190 #msi-cells = <1>;
5196 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt";
5204 #address-cells = <1>;
5205 #size-cells = <1>;
5207 compatible = "arm,armv7-timer-mem";
5211 frame-number = <0>;
5219 frame-number = <1>;
5226 frame-number = <2>;
5233 frame-number = <3>;
5240 frame-number = <4>;
5247 frame-number = <5>;
5254 frame-number = <6>;
5262 compatible = "qcom,rpmh-rsc";
5266 reg-names = "drv-0", "drv-1", "drv-2";
5270 qcom,tcs-offset = <0xd00>;
5271 qcom,drv-id = <2>;
5272 qcom,tcs-config = <ACTIVE_TCS 2>,
5277 apps_bcm_voter: bcm-voter {
5278 compatible = "qcom,bcm-voter";
5281 rpmhpd: power-controller {
5282 compatible = "qcom,sc7280-rpmhpd";
5283 #power-domain-cells = <1>;
5284 operating-points-v2 = <&rpmhpd_opp_table>;
5286 rpmhpd_opp_table: opp-table {
5287 compatible = "operating-points-v2";
5290 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
5294 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
5298 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
5302 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
5306 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
5310 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
5314 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
5318 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
5322 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
5327 rpmhcc: clock-controller {
5328 compatible = "qcom,sc7280-rpmh-clk";
5330 clock-names = "xo";
5331 #clock-cells = <1>;
5336 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3";
5339 clock-names = "xo", "alternate";
5340 #interconnect-cells = <1>;
5344 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss";
5352 interrupt-names = "dcvsh-irq-0",
5353 "dcvsh-irq-1",
5354 "dcvsh-irq-2";
5357 clock-names = "xo", "alternate";
5358 #freq-domain-cells = <1>;
5359 #clock-cells = <1>;
5363 thermal_zones: thermal-zones {
5364 cpu0-thermal {
5365 polling-delay-passive = <250>;
5366 polling-delay = <0>;
5368 thermal-sensors = <&tsens0 1>;
5371 cpu0_alert0: trip-point0 {
5377 cpu0_alert1: trip-point1 {
5383 cpu0_crit: cpu-crit {
5390 cooling-maps {
5393 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5400 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5408 cpu1-thermal {
5409 polling-delay-passive = <250>;
5410 polling-delay = <0>;
5412 thermal-sensors = <&tsens0 2>;
5415 cpu1_alert0: trip-point0 {
5421 cpu1_alert1: trip-point1 {
5427 cpu1_crit: cpu-crit {
5434 cooling-maps {
5437 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5444 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5452 cpu2-thermal {
5453 polling-delay-passive = <250>;
5454 polling-delay = <0>;
5456 thermal-sensors = <&tsens0 3>;
5459 cpu2_alert0: trip-point0 {
5465 cpu2_alert1: trip-point1 {
5471 cpu2_crit: cpu-crit {
5478 cooling-maps {
5481 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5488 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5496 cpu3-thermal {
5497 polling-delay-passive = <250>;
5498 polling-delay = <0>;
5500 thermal-sensors = <&tsens0 4>;
5503 cpu3_alert0: trip-point0 {
5509 cpu3_alert1: trip-point1 {
5515 cpu3_crit: cpu-crit {
5522 cooling-maps {
5525 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5532 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5540 cpu4-thermal {
5541 polling-delay-passive = <250>;
5542 polling-delay = <0>;
5544 thermal-sensors = <&tsens0 7>;
5547 cpu4_alert0: trip-point0 {
5553 cpu4_alert1: trip-point1 {
5559 cpu4_crit: cpu-crit {
5566 cooling-maps {
5569 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5576 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5584 cpu5-thermal {
5585 polling-delay-passive = <250>;
5586 polling-delay = <0>;
5588 thermal-sensors = <&tsens0 8>;
5591 cpu5_alert0: trip-point0 {
5597 cpu5_alert1: trip-point1 {
5603 cpu5_crit: cpu-crit {
5610 cooling-maps {
5613 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5620 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5628 cpu6-thermal {
5629 polling-delay-passive = <250>;
5630 polling-delay = <0>;
5632 thermal-sensors = <&tsens0 9>;
5635 cpu6_alert0: trip-point0 {
5641 cpu6_alert1: trip-point1 {
5647 cpu6_crit: cpu-crit {
5654 cooling-maps {
5657 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5664 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5672 cpu7-thermal {
5673 polling-delay-passive = <250>;
5674 polling-delay = <0>;
5676 thermal-sensors = <&tsens0 10>;
5679 cpu7_alert0: trip-point0 {
5685 cpu7_alert1: trip-point1 {
5691 cpu7_crit: cpu-crit {
5698 cooling-maps {
5701 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5708 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5716 cpu8-thermal {
5717 polling-delay-passive = <250>;
5718 polling-delay = <0>;
5720 thermal-sensors = <&tsens0 11>;
5723 cpu8_alert0: trip-point0 {
5729 cpu8_alert1: trip-point1 {
5735 cpu8_crit: cpu-crit {
5742 cooling-maps {
5745 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5752 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5760 cpu9-thermal {
5761 polling-delay-passive = <250>;
5762 polling-delay = <0>;
5764 thermal-sensors = <&tsens0 12>;
5767 cpu9_alert0: trip-point0 {
5773 cpu9_alert1: trip-point1 {
5779 cpu9_crit: cpu-crit {
5786 cooling-maps {
5789 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5796 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5804 cpu10-thermal {
5805 polling-delay-passive = <250>;
5806 polling-delay = <0>;
5808 thermal-sensors = <&tsens0 13>;
5811 cpu10_alert0: trip-point0 {
5817 cpu10_alert1: trip-point1 {
5823 cpu10_crit: cpu-crit {
5830 cooling-maps {
5833 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5840 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5848 cpu11-thermal {
5849 polling-delay-passive = <250>;
5850 polling-delay = <0>;
5852 thermal-sensors = <&tsens0 14>;
5855 cpu11_alert0: trip-point0 {
5861 cpu11_alert1: trip-point1 {
5867 cpu11_crit: cpu-crit {
5874 cooling-maps {
5877 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5884 cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
5892 aoss0-thermal {
5893 polling-delay-passive = <0>;
5894 polling-delay = <0>;
5896 thermal-sensors = <&tsens0 0>;
5899 aoss0_alert0: trip-point0 {
5905 aoss0_crit: aoss0-crit {
5913 aoss1-thermal {
5914 polling-delay-passive = <0>;
5915 polling-delay = <0>;
5917 thermal-sensors = <&tsens1 0>;
5920 aoss1_alert0: trip-point0 {
5926 aoss1_crit: aoss1-crit {
5934 cpuss0-thermal {
5935 polling-delay-passive = <0>;
5936 polling-delay = <0>;
5938 thermal-sensors = <&tsens0 5>;
5941 cpuss0_alert0: trip-point0 {
5946 cpuss0_crit: cluster0-crit {
5954 cpuss1-thermal {
5955 polling-delay-passive = <0>;
5956 polling-delay = <0>;
5958 thermal-sensors = <&tsens0 6>;
5961 cpuss1_alert0: trip-point0 {
5966 cpuss1_crit: cluster0-crit {
5974 gpuss0-thermal {
5975 polling-delay-passive = <100>;
5976 polling-delay = <0>;
5978 thermal-sensors = <&tsens1 1>;
5981 gpuss0_alert0: trip-point0 {
5987 gpuss0_crit: gpuss0-crit {
5994 cooling-maps {
5997 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6002 gpuss1-thermal {
6003 polling-delay-passive = <100>;
6004 polling-delay = <0>;
6006 thermal-sensors = <&tsens1 2>;
6009 gpuss1_alert0: trip-point0 {
6015 gpuss1_crit: gpuss1-crit {
6022 cooling-maps {
6025 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
6030 nspss0-thermal {
6031 polling-delay-passive = <0>;
6032 polling-delay = <0>;
6034 thermal-sensors = <&tsens1 3>;
6037 nspss0_alert0: trip-point0 {
6043 nspss0_crit: nspss0-crit {
6051 nspss1-thermal {
6052 polling-delay-passive = <0>;
6053 polling-delay = <0>;
6055 thermal-sensors = <&tsens1 4>;
6058 nspss1_alert0: trip-point0 {
6064 nspss1_crit: nspss1-crit {
6072 video-thermal {
6073 polling-delay-passive = <0>;
6074 polling-delay = <0>;
6076 thermal-sensors = <&tsens1 5>;
6079 video_alert0: trip-point0 {
6085 video_crit: video-crit {
6093 ddr-thermal {
6094 polling-delay-passive = <0>;
6095 polling-delay = <0>;
6097 thermal-sensors = <&tsens1 6>;
6100 ddr_alert0: trip-point0 {
6106 ddr_crit: ddr-crit {
6114 mdmss0-thermal {
6115 polling-delay-passive = <0>;
6116 polling-delay = <0>;
6118 thermal-sensors = <&tsens1 7>;
6121 mdmss0_alert0: trip-point0 {
6127 mdmss0_crit: mdmss0-crit {
6135 mdmss1-thermal {
6136 polling-delay-passive = <0>;
6137 polling-delay = <0>;
6139 thermal-sensors = <&tsens1 8>;
6142 mdmss1_alert0: trip-point0 {
6148 mdmss1_crit: mdmss1-crit {
6156 mdmss2-thermal {
6157 polling-delay-passive = <0>;
6158 polling-delay = <0>;
6160 thermal-sensors = <&tsens1 9>;
6163 mdmss2_alert0: trip-point0 {
6169 mdmss2_crit: mdmss2-crit {
6177 mdmss3-thermal {
6178 polling-delay-passive = <0>;
6179 polling-delay = <0>;
6181 thermal-sensors = <&tsens1 10>;
6184 mdmss3_alert0: trip-point0 {
6190 mdmss3_crit: mdmss3-crit {
6198 camera0-thermal {
6199 polling-delay-passive = <0>;
6200 polling-delay = <0>;
6202 thermal-sensors = <&tsens1 11>;
6205 camera0_alert0: trip-point0 {
6211 camera0_crit: camera0-crit {
6221 compatible = "arm,armv8-timer";