Lines Matching +full:0 +full:x01740000
78 #clock-cells = <0>;
84 #clock-cells = <0>;
95 reg = <0x0 0x004cd000 0x0 0x1000>;
99 reg = <0x0 0x80000000 0x0 0x600000>;
104 reg = <0x0 0x80600000 0x0 0x200000>;
109 reg = <0x0 0x80800000 0x0 0x60000>;
114 reg = <0x0 0x80860000 0x0 0x20000>;
120 reg = <0x0 0x80884000 0x0 0x10000>;
125 reg = <0x0 0x808ff000 0x0 0x1000>;
130 reg = <0x0 0x80900000 0x0 0x200000>;
136 reg = <0x0 0x80b00000 0x0 0x100000>;
140 reg = <0x0 0x80c00000 0x0 0xc00000>;
145 reg = <0x0 0x8b200000 0x0 0x500000>;
150 reg = <0 0x8b700000 0 0x10000>;
156 reg = <0x0 0x9c900000 0x0 0x280000>;
166 #size-cells = <0>;
168 CPU0: cpu@0 {
171 reg = <0x0 0x0>;
172 clocks = <&cpufreq_hw 0>;
181 qcom,freq-domain = <&cpufreq_hw 0>;
199 reg = <0x0 0x100>;
200 clocks = <&cpufreq_hw 0>;
209 qcom,freq-domain = <&cpufreq_hw 0>;
222 reg = <0x0 0x200>;
223 clocks = <&cpufreq_hw 0>;
232 qcom,freq-domain = <&cpufreq_hw 0>;
245 reg = <0x0 0x300>;
246 clocks = <&cpufreq_hw 0>;
255 qcom,freq-domain = <&cpufreq_hw 0>;
268 reg = <0x0 0x400>;
291 reg = <0x0 0x500>;
314 reg = <0x0 0x600>;
337 reg = <0x0 0x700>;
396 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
399 arm,psci-suspend-param = <0x40000003>;
406 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
409 arm,psci-suspend-param = <0x40000004>;
416 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
419 arm,psci-suspend-param = <0x40000003>;
429 arm,psci-suspend-param = <0x40000004>;
436 CLUSTER_SLEEP_0: cluster-sleep-0 {
439 arm,psci-suspend-param = <0x40003444>;
656 reg = <0 0x80000000 0 0>;
686 qcom,local-pid = <0>;
710 qcom,local-pid = <0>;
734 qcom,local-pid = <0>;
769 qcom,local-pid = <0>;
848 soc: soc@0 {
851 ranges = <0 0 0 0 0x10 0>;
852 dma-ranges = <0 0 0 0 0x10 0>;
857 reg = <0 0x00100000 0 0x1f0000>;
860 <0>, <&pcie1_lane>,
861 <0>, <0>, <0>,
876 reg = <0 0x00408000 0 0x1000>;
885 reg = <0 0x00784000 0 0xa20>,
886 <0 0x00780000 0 0xa20>,
887 <0 0x00782000 0 0x120>,
888 <0 0x00786000 0 0x1fff>;
896 reg = <0x1e9 0x2>;
904 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
908 reg = <0 0x007c4000 0 0x1000>,
909 <0 0x007c5000 0 0x1000>;
912 iommus = <&apps_smmu 0xc0 0x0>;
921 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
922 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>;
931 qcom,dll-config = <0x0007642c>;
932 qcom,ddr-config = <0x80040868>;
948 opp-avg-kBps = <100000 0>;
955 opp-avg-kBps = <390000 0>;
963 reg = <0 0x00900000 0 0x60000>;
977 dma-channel-mask = <0x7f>;
978 iommus = <&apps_smmu 0x0136 0x0>;
984 reg = <0 0x009c0000 0 0x2000>;
991 iommus = <&apps_smmu 0x123 0x0>;
996 reg = <0 0x00980000 0 0x4000>;
1000 pinctrl-0 = <&qup_i2c0_data_clk>;
1003 #size-cells = <0>;
1004 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1005 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1006 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1011 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1012 <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1019 reg = <0 0x00980000 0 0x4000>;
1023 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
1026 #size-cells = <0>;
1029 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1030 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1032 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1033 <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1040 reg = <0 0x00980000 0 0x4000>;
1044 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
1048 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1049 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1056 reg = <0 0x00984000 0 0x4000>;
1060 pinctrl-0 = <&qup_i2c1_data_clk>;
1063 #size-cells = <0>;
1064 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1065 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1066 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1071 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1079 reg = <0 0x00984000 0 0x4000>;
1083 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
1086 #size-cells = <0>;
1089 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1090 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1092 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1100 reg = <0 0x00984000 0 0x4000>;
1104 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
1108 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1109 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1116 reg = <0 0x00988000 0 0x4000>;
1120 pinctrl-0 = <&qup_i2c2_data_clk>;
1123 #size-cells = <0>;
1124 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1125 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1126 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1131 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1139 reg = <0 0x00988000 0 0x4000>;
1143 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
1146 #size-cells = <0>;
1149 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1150 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1152 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1160 reg = <0 0x00988000 0 0x4000>;
1164 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
1168 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1169 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1176 reg = <0 0x0098c000 0 0x4000>;
1180 pinctrl-0 = <&qup_i2c3_data_clk>;
1183 #size-cells = <0>;
1184 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1185 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1186 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1191 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1199 reg = <0 0x0098c000 0 0x4000>;
1203 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
1206 #size-cells = <0>;
1209 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1210 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1212 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1220 reg = <0 0x0098c000 0 0x4000>;
1224 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
1228 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1229 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1236 reg = <0 0x00990000 0 0x4000>;
1240 pinctrl-0 = <&qup_i2c4_data_clk>;
1243 #size-cells = <0>;
1244 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1245 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1246 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1251 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1259 reg = <0 0x00990000 0 0x4000>;
1263 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
1266 #size-cells = <0>;
1269 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1270 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1272 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1280 reg = <0 0x00990000 0 0x4000>;
1284 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
1288 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1289 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1296 reg = <0 0x00994000 0 0x4000>;
1300 pinctrl-0 = <&qup_i2c5_data_clk>;
1303 #size-cells = <0>;
1304 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1305 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1306 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1311 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1319 reg = <0 0x00994000 0 0x4000>;
1323 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
1326 #size-cells = <0>;
1329 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1330 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1332 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1340 reg = <0 0x00994000 0 0x4000>;
1344 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
1348 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1349 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1356 reg = <0 0x00998000 0 0x4000>;
1360 pinctrl-0 = <&qup_i2c6_data_clk>;
1363 #size-cells = <0>;
1364 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1365 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1366 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1371 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
1379 reg = <0 0x00998000 0 0x4000>;
1383 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
1386 #size-cells = <0>;
1389 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1390 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1392 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
1400 reg = <0 0x00998000 0 0x4000>;
1404 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
1408 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1409 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1416 reg = <0 0x0099c000 0 0x4000>;
1420 pinctrl-0 = <&qup_i2c7_data_clk>;
1423 #size-cells = <0>;
1424 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1425 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
1426 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1431 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
1439 reg = <0 0x0099c000 0 0x4000>;
1443 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
1446 #size-cells = <0>;
1449 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1450 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1452 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
1460 reg = <0 0x0099c000 0 0x4000>;
1464 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
1468 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
1469 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
1478 reg = <0 0x00a00000 0 0x60000>;
1492 dma-channel-mask = <0x1e>;
1493 iommus = <&apps_smmu 0x56 0x0>;
1499 reg = <0 0x00ac0000 0 0x2000>;
1506 iommus = <&apps_smmu 0x43 0x0>;
1511 reg = <0 0x00a80000 0 0x4000>;
1515 pinctrl-0 = <&qup_i2c8_data_clk>;
1518 #size-cells = <0>;
1519 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1520 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1521 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1526 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1527 <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1534 reg = <0 0x00a80000 0 0x4000>;
1538 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1541 #size-cells = <0>;
1544 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1545 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1547 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1548 <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1555 reg = <0 0x00a80000 0 0x4000>;
1559 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
1563 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1564 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1571 reg = <0 0x00a84000 0 0x4000>;
1575 pinctrl-0 = <&qup_i2c9_data_clk>;
1578 #size-cells = <0>;
1579 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1580 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1581 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1586 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1594 reg = <0 0x00a84000 0 0x4000>;
1598 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1601 #size-cells = <0>;
1604 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1605 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1607 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1615 reg = <0 0x00a84000 0 0x4000>;
1619 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
1623 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1624 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1631 reg = <0 0x00a88000 0 0x4000>;
1635 pinctrl-0 = <&qup_i2c10_data_clk>;
1638 #size-cells = <0>;
1639 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1640 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1641 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1646 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1654 reg = <0 0x00a88000 0 0x4000>;
1658 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1661 #size-cells = <0>;
1664 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1665 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1667 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1675 reg = <0 0x00a88000 0 0x4000>;
1679 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1684 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1691 reg = <0 0x00a8c000 0 0x4000>;
1695 pinctrl-0 = <&qup_i2c11_data_clk>;
1698 #size-cells = <0>;
1699 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1700 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1701 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1706 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1714 reg = <0 0x00a8c000 0 0x4000>;
1718 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1721 #size-cells = <0>;
1724 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1725 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1727 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1735 reg = <0 0x00a8c000 0 0x4000>;
1739 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
1743 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1744 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1751 reg = <0 0x00a90000 0 0x4000>;
1755 pinctrl-0 = <&qup_i2c12_data_clk>;
1758 #size-cells = <0>;
1759 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1760 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1761 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1766 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1774 reg = <0 0x00a90000 0 0x4000>;
1778 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1781 #size-cells = <0>;
1784 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1785 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1787 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1795 reg = <0 0x00a90000 0 0x4000>;
1799 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
1803 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1804 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1811 reg = <0 0x00a94000 0 0x4000>;
1815 pinctrl-0 = <&qup_i2c13_data_clk>;
1818 #size-cells = <0>;
1819 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1820 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1821 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1826 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1834 reg = <0 0x00a94000 0 0x4000>;
1838 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1841 #size-cells = <0>;
1844 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1845 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1847 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1855 reg = <0 0x00a94000 0 0x4000>;
1859 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
1863 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1864 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1871 reg = <0 0x00a98000 0 0x4000>;
1875 pinctrl-0 = <&qup_i2c14_data_clk>;
1878 #size-cells = <0>;
1879 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1880 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1881 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1886 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1894 reg = <0 0x00a98000 0 0x4000>;
1898 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
1901 #size-cells = <0>;
1904 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1905 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1907 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
1915 reg = <0 0x00a98000 0 0x4000>;
1919 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
1923 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1924 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1931 reg = <0 0x00a9c000 0 0x4000>;
1935 pinctrl-0 = <&qup_i2c15_data_clk>;
1938 #size-cells = <0>;
1939 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1940 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
1941 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1946 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
1954 reg = <0 0x00a9c000 0 0x4000>;
1958 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
1961 #size-cells = <0>;
1964 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1965 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1967 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
1975 reg = <0 0x00a9c000 0 0x4000>;
1979 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
1983 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
1984 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
1991 reg = <0 0x01500000 0 0x1000>;
1998 reg = <0 0x01502000 0 0x1000>;
2005 reg = <0 0x01580000 0 0x4>;
2012 reg = <0 0x01680000 0 0x15480>;
2020 reg = <0 0x016e0000 0 0x1c080>;
2026 reg = <0 0x01700000 0 0x2b080>;
2033 reg = <0 0x01740000 0 0x1e080>;
2041 reg = <0 0x17a10040 0 0x0>;
2042 iommus = <&apps_smmu 0x1c00 0x1>;
2078 qcom,smem-states = <&wlan_smp2p_out 0>;
2084 reg = <0 0x01c08000 0 0x3000>,
2085 <0 0x40000000 0 0xf1d>,
2086 <0 0x40000f20 0 0xa8>,
2087 <0 0x40001000 0 0x1000>,
2088 <0 0x40100000 0 0x100000>;
2093 bus-range = <0x00 0xff>;
2099 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,
2100 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
2113 interrupt-map-mask = <0 0 0 0x7>;
2114 interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>,
2115 <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>,
2116 <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>,
2117 <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>;
2159 pinctrl-0 = <&pcie1_clkreq_n>;
2163 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
2164 <0x100 &apps_smmu 0x1c81 0x1>;
2171 reg = <0 0x01c0e000 0 0x1c0>;
2190 reg = <0 0x01c0e200 0 0x170>,
2191 <0 0x01c0e400 0 0x200>,
2192 <0 0x01c0ea00 0 0x1f0>,
2193 <0 0x01c0e600 0 0x170>,
2194 <0 0x01c0e800 0 0x200>,
2195 <0 0x01c0ee00 0 0xf4>;
2199 #phy-cells = <0>;
2200 #clock-cells = <0>;
2208 iommus = <&apps_smmu 0x480 0x0>,
2209 <&apps_smmu 0x482 0x0>;
2210 reg = <0 0x01e40000 0 0x8000>,
2211 <0 0x01e50000 0 0x4ad0>,
2212 <0 0x01e04000 0 0x23000>;
2219 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2229 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
2230 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
2236 qcom,smem-states = <&ipa_smp2p_out 0>,
2246 reg = <0 0x01f40000 0 0x20000>;
2252 reg = <0 0x01f60000 0 0x20000>;
2257 reg = <0 0x01fc0000 0 0x30000>;
2262 reg = <0 0x03000000 0 0x40>,
2263 <0 0x03c04000 0 0x4>;
2273 reg = <0 0x03200000 0 0x1000>;
2276 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>;
2287 #clock-cells = <0>;
2295 reg = <0 0x03210000 0 0x2000>;
2301 qcom,din-ports = <0>;
2307 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>;
2308 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>;
2309 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>;
2310 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>;
2311 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>;
2312 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>;
2313 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>;
2314 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>;
2315 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>;
2319 #size-cells = <0>;
2326 reg = <0 0x03220000 0 0x1000>;
2329 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>;
2340 #clock-cells = <0>;
2348 reg = <0 0x03230000 0 0x2000>;
2356 qcom,dout-ports = <0>;
2361 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>;
2362 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>;
2363 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>;
2364 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>;
2365 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>;
2366 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>;
2367 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>;
2368 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>;
2369 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>;
2373 #size-cells = <0>;
2380 reg = <0 0x03300000 0 0x30000>,
2381 <0 0x032a9000 0 0x1000>;
2393 reg = <0 0x03370000 0 0x1000>;
2396 pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>;
2405 #clock-cells = <0>;
2413 reg = <0 0x03380000 0 0x30000>;
2425 reg = <0 0x03900000 0 0x50000>;
2437 reg = <0 0x03987000 0 0x68000>,
2438 <0 0x03b00000 0 0x29000>,
2439 <0 0x03260000 0 0xc000>,
2440 <0 0x03280000 0 0x29000>,
2441 <0 0x03340000 0 0x29000>,
2442 <0 0x0336c000 0 0x3000>;
2450 iommus = <&apps_smmu 0x1820 0>,
2451 <&apps_smmu 0x1821 0>,
2452 <&apps_smmu 0x1832 0>;
2481 #size-cells = <0>;
2497 reg = <0 0x03c00000 0 0x28>;
2506 reg = <0 0x03c40000 0 0xf080>;
2514 reg = <0 0x033c0000 0x0 0x20000>,
2515 <0 0x03550000 0x0 0x10000>;
2519 gpio-ranges = <&lpass_tlmm 0 0 15>;
2564 reg = <0 0x03d00000 0 0x40000>,
2565 <0 0x03d9e000 0 0x1000>,
2566 <0 0x03d61000 0 0x800>;
2571 iommus = <&adreno_smmu 0 0x400>,
2572 <&adreno_smmu 1 0x400>;
2575 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2589 opp-supported-hw = <0x03>;
2596 opp-supported-hw = <0x03>;
2600 opp-550000000-0 {
2604 opp-supported-hw = <0x01>;
2611 opp-supported-hw = <0x02>;
2618 opp-supported-hw = <0x02>;
2625 opp-supported-hw = <0x02>;
2632 opp-supported-hw = <0x02>;
2639 opp-supported-hw = <0x02>;
2646 opp-supported-hw = <0x02>;
2653 reg = <0 0x03d6a000 0 0x34000>,
2654 <0 0x3de0000 0 0x10000>,
2655 <0 0x0b290000 0 0x10000>;
2678 iommus = <&adreno_smmu 5 0x400>;
2693 reg = <0 0x03d90000 0 0x9000>;
2707 reg = <0x0 0x0117f000 0x0 0x1000>,
2708 <0x0 0x01112000 0x0 0x6000>;
2714 reg = <0 0x03da0000 0 0x20000>;
2751 reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>;
2755 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2774 qcom,smem-states = <&modem_smp2p_out 0>;
2792 reg = <0 0x06002000 0 0x1000>,
2793 <0 0x16280000 0 0x180000>;
2810 reg = <0 0x06041000 0 0x1000>;
2825 #size-cells = <0>;
2838 reg = <0 0x06042000 0 0x1000>;
2853 #size-cells = <0>;
2866 reg = <0 0x06045000 0 0x1000>;
2881 #size-cells = <0>;
2883 port@0 {
2884 reg = <0>;
2901 reg = <0 0x06046000 0 0x1000>;
2925 reg = <0 0x06048000 0 0x1000>;
2926 iommus = <&apps_smmu 0x04c0 0>;
2943 reg = <0 0x06b04000 0 0x1000>;
2958 #size-cells = <0>;
2971 reg = <0 0x06b05000 0 0x1000>;
2995 reg = <0 0x06b06000 0 0x1000>;
3020 reg = <0 0x07040000 0 0x1000>;
3040 reg = <0 0x07140000 0 0x1000>;
3060 reg = <0 0x07240000 0 0x1000>;
3080 reg = <0 0x07340000 0 0x1000>;
3100 reg = <0 0x07440000 0 0x1000>;
3120 reg = <0 0x07540000 0 0x1000>;
3140 reg = <0 0x07640000 0 0x1000>;
3160 reg = <0 0x07740000 0 0x1000>;
3180 reg = <0 0x07800000 0 0x1000>;
3195 #size-cells = <0>;
3197 port@0 {
3198 reg = <0>;
3257 reg = <0 0x07810000 0 0x1000>;
3282 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
3286 reg = <0 0x08804000 0 0x1000>;
3288 iommus = <&apps_smmu 0x100 0x0>;
3297 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
3298 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>;
3306 qcom,dll-config = <0x0007642c>;
3317 opp-avg-kBps = <100000 0>;
3324 opp-avg-kBps = <200000 0>;
3332 reg = <0 0x088e3000 0 0x400>;
3334 #phy-cells = <0>;
3345 reg = <0 0x088e4000 0 0x400>;
3347 #phy-cells = <0>;
3357 reg = <0 0x088e8000 0 0x3000>;
3379 reg = <0 0x08cf8800 0 0x400>;
3413 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>,
3414 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>;
3419 reg = <0 0x08c00000 0 0xe000>;
3421 iommus = <&apps_smmu 0xa0 0x0>;
3439 reg = <0 0x088dc000 0 0x1000>;
3440 iommus = <&apps_smmu 0x20 0x0>;
3442 #size-cells = <0>;
3447 interconnects = <&gem_noc MASTER_APPSS_PROC 0
3448 &cnoc2 SLAVE_QSPI_0 0>;
3457 reg = <0 0x08a00000 0 0x10000>;
3460 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
3483 qcom,smem-states = <&wpss_smp2p_out 0>;
3490 qcom,halt-regs = <&tcsr_1 0x17000>;
3508 reg = <0 0x09091000 0 0x1000>;
3519 opp-0 {
3548 reg = <0 0x090b6400 0 0x600>;
3558 opp-0 {
3583 reg = <0 0x090e0000 0 0x5080>;
3590 reg = <0 0x09100000 0 0xe2200>;
3598 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
3599 <0 0x09600000 0 0x58000>;
3606 reg = <0 0x88e0000 0 0x2000>,
3607 <0 0x88e2000 0 0x1000>;
3614 #size-cells = <0>;
3616 port@0 {
3617 reg = <0>;
3626 reg = <0 0x0a0c0000 0 0x10000>;
3634 reg = <0 0x0a6f8800 0 0x400>;
3670 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>,
3671 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>;
3678 reg = <0 0x0a600000 0 0xe000>;
3680 iommus = <&apps_smmu 0xe0 0x0>;
3692 reg = <0 0x0aa00000 0 0xd0600>;
3709 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
3710 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
3713 iommus = <&apps_smmu 0x2180 0x20>,
3714 <&apps_smmu 0x2184 0x20>;
3726 iommus = <&apps_smmu 0x21a2 0x0>;
3761 reg = <0 0x0aaf0000 0 0x10000>;
3772 reg = <0 0x0ad00000 0 0x10000>;
3784 reg = <0 0x0af00000 0 0x20000>;
3787 <&mdss_dsi_phy 0>,
3791 <&mdss_edp_phy 0>,
3808 reg = <0 0x0ae00000 0 0x1000>;
3824 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3827 iommus = <&apps_smmu 0x900 0x402>;
3837 reg = <0 0x0ae01000 0 0x8f030>,
3838 <0 0x0aeb0000 0 0x2008>;
3861 interrupts = <0>;
3865 #size-cells = <0>;
3867 port@0 {
3868 reg = <0>;
3917 reg = <0 0x0ae94000 0 0x400>;
3937 assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>;
3945 #size-cells = <0>;
3951 #size-cells = <0>;
3953 port@0 {
3954 reg = <0>;
3989 reg = <0 0x0ae94400 0 0x200>,
3990 <0 0x0ae94600 0 0x280>,
3991 <0 0x0ae94900 0 0x280>;
3997 #phy-cells = <0>;
4009 pinctrl-0 = <&edp_hot_plug_det>;
4011 reg = <0 0x0aea0000 0 0x200>,
4012 <0 0x0aea0200 0 0x200>,
4013 <0 0x0aea0400 0 0xc00>,
4014 <0 0x0aea1000 0 0x400>;
4031 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
4043 #size-cells = <0>;
4045 port@0 {
4046 reg = <0>;
4086 reg = <0 0x0aec2a00 0 0x19c>,
4087 <0 0x0aec2200 0 0xa0>,
4088 <0 0x0aec2600 0 0xa0>,
4089 <0 0x0aec2000 0 0x1c0>;
4097 #phy-cells = <0>;
4105 reg = <0 0x0ae90000 0 0x200>,
4106 <0 0x0ae90200 0 0x200>,
4107 <0 0x0ae90400 0 0xc00>,
4108 <0 0x0ae91000 0 0x400>,
4109 <0 0x0ae91400 0 0x400>;
4134 #sound-dai-cells = <0>;
4140 #size-cells = <0>;
4142 port@0 {
4143 reg = <0>;
4183 reg = <0 0x0b220000 0 0x30000>;
4184 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
4196 reg = <0 0x0b5e0000 0 0x20000>;
4203 reg = <0 0x0c263000 0 0x1ff>, /* TM */
4204 <0 0x0c222000 0 0x1ff>; /* SROT */
4214 reg = <0 0x0c265000 0 0x1ff>, /* TM */
4215 <0 0x0c223000 0 0x1ff>; /* SROT */
4225 reg = <0 0x0c2a0000 0 0x31000>;
4231 reg = <0 0x0c300000 0 0x400>;
4238 #clock-cells = <0>;
4243 reg = <0 0x0c3f0000 0 0x400>;
4248 reg = <0 0x0c440000 0 0x1100>,
4249 <0 0x0c600000 0 0x2000000>,
4250 <0 0x0e600000 0 0x100000>,
4251 <0 0x0e700000 0 0xa0000>,
4252 <0 0x0c40a000 0 0x26000>;
4256 qcom,ee = <0>;
4257 qcom,channel = <0>;
4259 #size-cells = <0>;
4266 reg = <0 0x0f100000 0 0x300000>;
4272 gpio-ranges = <&tlmm 0 0 175>;
5073 reg = <0 0x146a5000 0 0x6000>;
5078 ranges = <0 0 0x146a5000 0x6000>;
5082 reg = <0x594c 0xc8>;
5088 reg = <0 0x15000000 0 0x100000>;
5177 reg = <0 0x17a00000 0 0x10000>, /* GICD */
5178 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
5188 reg = <0 0x17a40000 0 0x20000>;
5197 reg = <0 0x17c10000 0 0x1000>;
5199 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
5206 ranges = <0 0 0 0x20000000>;
5208 reg = <0 0x17c20000 0 0x1000>;
5211 frame-number = <0>;
5214 reg = <0x17c21000 0x1000>,
5215 <0x17c22000 0x1000>;
5221 reg = <0x17c23000 0x1000>;
5228 reg = <0x17c25000 0x1000>;
5235 reg = <0x17c27000 0x1000>;
5242 reg = <0x17c29000 0x1000>;
5249 reg = <0x17c2b000 0x1000>;
5256 reg = <0x17c2d000 0x1000>;
5263 reg = <0 0x18200000 0 0x10000>,
5264 <0 0x18210000 0 0x10000>,
5265 <0 0x18220000 0 0x10000>;
5266 reg-names = "drv-0", "drv-1", "drv-2";
5270 qcom,tcs-offset = <0xd00>;
5337 reg = <0 0x18590000 0 0x1000>;
5345 reg = <0 0x18591000 0 0x1000>,
5346 <0 0x18592000 0 0x1000>,
5347 <0 0x18593000 0 0x1000>;
5352 interrupt-names = "dcvsh-irq-0",
5366 polling-delay = <0>;
5385 hysteresis = <0>;
5410 polling-delay = <0>;
5429 hysteresis = <0>;
5454 polling-delay = <0>;
5473 hysteresis = <0>;
5498 polling-delay = <0>;
5517 hysteresis = <0>;
5542 polling-delay = <0>;
5561 hysteresis = <0>;
5586 polling-delay = <0>;
5605 hysteresis = <0>;
5630 polling-delay = <0>;
5649 hysteresis = <0>;
5674 polling-delay = <0>;
5693 hysteresis = <0>;
5718 polling-delay = <0>;
5737 hysteresis = <0>;
5762 polling-delay = <0>;
5781 hysteresis = <0>;
5806 polling-delay = <0>;
5825 hysteresis = <0>;
5850 polling-delay = <0>;
5869 hysteresis = <0>;
5893 polling-delay-passive = <0>;
5894 polling-delay = <0>;
5896 thermal-sensors = <&tsens0 0>;
5907 hysteresis = <0>;
5914 polling-delay-passive = <0>;
5915 polling-delay = <0>;
5917 thermal-sensors = <&tsens1 0>;
5928 hysteresis = <0>;
5935 polling-delay-passive = <0>;
5936 polling-delay = <0>;
5948 hysteresis = <0>;
5955 polling-delay-passive = <0>;
5956 polling-delay = <0>;
5968 hysteresis = <0>;
5976 polling-delay = <0>;
5989 hysteresis = <0>;
6004 polling-delay = <0>;
6017 hysteresis = <0>;
6031 polling-delay-passive = <0>;
6032 polling-delay = <0>;
6045 hysteresis = <0>;
6052 polling-delay-passive = <0>;
6053 polling-delay = <0>;
6066 hysteresis = <0>;
6073 polling-delay-passive = <0>;
6074 polling-delay = <0>;
6087 hysteresis = <0>;
6094 polling-delay-passive = <0>;
6095 polling-delay = <0>;
6108 hysteresis = <0>;
6115 polling-delay-passive = <0>;
6116 polling-delay = <0>;
6129 hysteresis = <0>;
6136 polling-delay-passive = <0>;
6137 polling-delay = <0>;
6150 hysteresis = <0>;
6157 polling-delay-passive = <0>;
6158 polling-delay = <0>;
6171 hysteresis = <0>;
6178 polling-delay-passive = <0>;
6179 polling-delay = <0>;
6192 hysteresis = <0>;
6199 polling-delay-passive = <0>;
6200 polling-delay = <0>;
6213 hysteresis = <0>;