Lines Matching +full:phy +full:- +full:qcom +full:- +full:qusb2
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&intc>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 sleep_clk: sleep-clk {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
26 xo_board_clk: xo-board-clk {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
38 compatible = "arm,cortex-a73";
40 enable-method = "psci";
41 next-level-cache = <&L2_0>;
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu_opp_table>;
45 cpu-supply = <&ipq9574_s1>;
46 #cooling-cells = <2>;
51 compatible = "arm,cortex-a73";
53 enable-method = "psci";
54 next-level-cache = <&L2_0>;
56 clock-names = "cpu";
57 operating-points-v2 = <&cpu_opp_table>;
58 cpu-supply = <&ipq9574_s1>;
59 #cooling-cells = <2>;
64 compatible = "arm,cortex-a73";
66 enable-method = "psci";
67 next-level-cache = <&L2_0>;
69 clock-names = "cpu";
70 operating-points-v2 = <&cpu_opp_table>;
71 cpu-supply = <&ipq9574_s1>;
72 #cooling-cells = <2>;
77 compatible = "arm,cortex-a73";
79 enable-method = "psci";
80 next-level-cache = <&L2_0>;
82 clock-names = "cpu";
83 operating-points-v2 = <&cpu_opp_table>;
84 cpu-supply = <&ipq9574_s1>;
85 #cooling-cells = <2>;
88 L2_0: l2-cache {
90 cache-level = <2>;
91 cache-unified;
97 compatible = "qcom,scm-ipq9574", "qcom,scm";
98 qcom,dload-mode = <&tcsr 0x6100>;
108 cpu_opp_table: opp-table-cpu {
109 compatible = "operating-points-v2";
110 opp-shared;
112 opp-936000000 {
113 opp-hz = /bits/ 64 <936000000>;
114 opp-microvolt = <725000>;
115 clock-latency-ns = <200000>;
118 opp-1104000000 {
119 opp-hz = /bits/ 64 <1104000000>;
120 opp-microvolt = <787500>;
121 clock-latency-ns = <200000>;
124 opp-1416000000 {
125 opp-hz = /bits/ 64 <1416000000>;
126 opp-microvolt = <862500>;
127 clock-latency-ns = <200000>;
130 opp-1488000000 {
131 opp-hz = /bits/ 64 <1488000000>;
132 opp-microvolt = <925000>;
133 clock-latency-ns = <200000>;
136 opp-1800000000 {
137 opp-hz = /bits/ 64 <1800000000>;
138 opp-microvolt = <987500>;
139 clock-latency-ns = <200000>;
142 opp-2208000000 {
143 opp-hz = /bits/ 64 <2208000000>;
144 opp-microvolt = <1062500>;
145 clock-latency-ns = <200000>;
150 compatible = "arm,cortex-a73-pmu";
155 compatible = "arm,psci-1.0";
160 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";
162 glink-edge {
163 compatible = "qcom,glink-rpm";
165 qcom,rpm-msg-ram = <&rpm_msg_ram>;
168 rpm_requests: rpm-requests {
169 compatible = "qcom,rpm-ipq9574";
170 qcom,glink-channels = "rpm_requests";
175 reserved-memory {
176 #address-cells = <2>;
177 #size-cells = <2>;
182 no-map;
187 no-map;
192 no-map;
196 compatible = "qcom,smem";
199 no-map;
204 compatible = "simple-bus";
205 #address-cells = <1>;
206 #size-cells = <1>;
210 compatible = "qcom,rpm-msg-ram";
215 compatible = "qcom,prng-ee";
218 clock-names = "core";
222 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
224 #address-cells = <1>;
225 #size-cells = <1>;
228 cryptobam: dma-controller@704000 {
229 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
232 #dma-cells = <1>;
233 qcom,ee = <1>;
234 qcom,num-ees = <4>;
235 num-channels = <16>;
236 qcom,controlled-remotely;
240 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
245 clock-names = "iface", "bus", "core";
247 dma-names = "rx", "tx";
250 tsens: thermal-sensor@4a9000 {
251 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
255 interrupt-names = "combined";
256 #qcom,sensors = <16>;
257 #thermal-sensor-cells = <1>;
261 compatible = "qcom,ipq9574-tlmm";
264 gpio-controller;
265 #gpio-cells = <2>;
266 gpio-ranges = <&tlmm 0 0 65>;
267 interrupt-controller;
268 #interrupt-cells = <2>;
270 uart2_pins: uart2-state {
273 drive-strength = <8>;
274 bias-disable;
278 gcc: clock-controller@1800000 {
279 compatible = "qcom,ipq9574-gcc";
289 #clock-cells = <1>;
290 #reset-cells = <1>;
291 #power-domain-cells = <1>;
295 compatible = "qcom,tcsr-mutex";
297 #hwlock-cells = <1>;
301 compatible = "qcom,tcsr-ipq9574", "syscon";
306 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
308 reg-names = "hc", "cqhci";
312 interrupt-names = "hc_irq", "pwr_irq";
317 clock-names = "iface", "core", "xo";
318 non-removable;
322 blsp_dma: dma-controller@7884000 {
323 compatible = "qcom,bam-v1.7.0";
327 clock-names = "bam_clk";
328 #dma-cells = <1>;
329 qcom,ee = <0>;
333 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
338 clock-names = "core", "iface";
343 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
348 clock-names = "core", "iface";
353 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
358 clock-names = "core", "iface";
363 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
368 clock-names = "core", "iface";
373 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
378 clock-names = "core", "iface";
383 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
388 clock-names = "core", "iface";
393 compatible = "qcom,spi-qup-v2.2.1";
395 #address-cells = <1>;
396 #size-cells = <0>;
400 clock-names = "core", "iface";
402 dma-names = "tx", "rx";
407 compatible = "qcom,i2c-qup-v2.2.1";
409 #address-cells = <1>;
410 #size-cells = <0>;
414 clock-names = "core", "iface";
415 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
416 assigned-clock-rates = <50000000>;
418 dma-names = "tx", "rx";
423 compatible = "qcom,spi-qup-v2.2.1";
425 #address-cells = <1>;
426 #size-cells = <0>;
430 clock-names = "core", "iface";
432 dma-names = "tx", "rx";
437 compatible = "qcom,i2c-qup-v2.2.1";
439 #address-cells = <1>;
440 #size-cells = <0>;
444 clock-names = "core", "iface";
445 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
446 assigned-clock-rates = <50000000>;
448 dma-names = "tx", "rx";
453 compatible = "qcom,spi-qup-v2.2.1";
455 #address-cells = <1>;
456 #size-cells = <0>;
460 clock-names = "core", "iface";
462 dma-names = "tx", "rx";
467 compatible = "qcom,i2c-qup-v2.2.1";
469 #address-cells = <1>;
470 #size-cells = <0>;
474 clock-names = "core", "iface";
475 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
476 assigned-clock-rates = <50000000>;
478 dma-names = "tx", "rx";
483 compatible = "qcom,spi-qup-v2.2.1";
485 #address-cells = <1>;
486 #size-cells = <0>;
488 spi-max-frequency = <50000000>;
491 clock-names = "core", "iface";
493 dma-names = "tx", "rx";
498 compatible = "qcom,i2c-qup-v2.2.1";
500 #address-cells = <1>;
501 #size-cells = <0>;
505 clock-names = "core", "iface";
506 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
507 assigned-clock-rates = <50000000>;
509 dma-names = "tx", "rx";
514 compatible = "qcom,spi-qup-v2.2.1";
516 #address-cells = <1>;
517 #size-cells = <0>;
521 clock-names = "core", "iface";
523 dma-names = "tx", "rx";
527 usb_0_qusbphy: phy@7b000 {
528 compatible = "qcom,ipq9574-qusb2-phy";
530 #phy-cells = <0>;
534 clock-names = "cfg_ahb",
541 usb_0_qmpphy: phy@7d000 {
542 compatible = "qcom,ipq9574-qmp-usb3-phy";
544 #phy-cells = <0>;
550 clock-names = "aux",
557 reset-names = "phy",
560 #clock-cells = <0>;
561 clock-output-names = "usb0_pipe_clk";
567 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
569 #address-cells = <1>;
570 #size-cells = <1>;
579 clock-names = "cfg_noc",
585 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
587 assigned-clock-rates = <200000000>,
590 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
591 interrupt-names = "pwr_event";
600 clock-names = "ref";
603 phy-names = "usb2-phy", "usb3-phy";
604 tx-fifo-resize;
605 snps,is-utmi-l1-suspend;
606 snps,hird-threshold = /bits/ 8 <0x0>;
612 intc: interrupt-controller@b000000 {
613 compatible = "qcom,msm-qgic2";
618 #address-cells = <1>;
619 #size-cells = <1>;
620 interrupt-controller;
621 #interrupt-cells = <3>;
626 compatible = "arm,gic-v2m-frame";
628 msi-controller;
632 compatible = "arm,gic-v2m-frame";
634 msi-controller;
638 compatible = "arm,gic-v2m-frame";
640 msi-controller;
645 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
649 timeout-sec = <30>;
653 compatible = "qcom,ipq9574-apcs-apps-global",
654 "qcom,ipq6018-apcs-apps-global";
656 #clock-cells = <1>;
658 clock-names = "pll", "xo";
659 #mbox-cells = <1>;
663 compatible = "qcom,ipq9574-a73pll";
665 #clock-cells = <0>;
667 clock-names = "xo";
671 compatible = "arm,armv7-timer-mem";
673 #address-cells = <1>;
674 #size-cells = <1>;
680 frame-number = <0>;
687 frame-number = <1>;
694 frame-number = <2>;
701 frame-number = <3>;
708 frame-number = <4>;
715 frame-number = <5>;
722 frame-number = <6>;
729 thermal-zones {
730 nss-top-thermal {
731 polling-delay-passive = <0>;
732 polling-delay = <0>;
733 thermal-sensors = <&tsens 3>;
736 nss-top-critical {
744 ubi-0-thermal {
745 polling-delay-passive = <0>;
746 polling-delay = <0>;
747 thermal-sensors = <&tsens 4>;
750 ubi_0-critical {
758 ubi-1-thermal {
759 polling-delay-passive = <0>;
760 polling-delay = <0>;
761 thermal-sensors = <&tsens 5>;
764 ubi_1-critical {
772 ubi-2-thermal {
773 polling-delay-passive = <0>;
774 polling-delay = <0>;
775 thermal-sensors = <&tsens 6>;
778 ubi_2-critical {
786 ubi-3-thermal {
787 polling-delay-passive = <0>;
788 polling-delay = <0>;
789 thermal-sensors = <&tsens 7>;
792 ubi_3-critical {
800 cpuss0-thermal {
801 polling-delay-passive = <0>;
802 polling-delay = <0>;
803 thermal-sensors = <&tsens 8>;
806 cpu-critical {
814 cpuss1-thermal {
815 polling-delay-passive = <0>;
816 polling-delay = <0>;
817 thermal-sensors = <&tsens 9>;
820 cpu-critical {
828 cpu0-thermal {
829 polling-delay-passive = <0>;
830 polling-delay = <0>;
831 thermal-sensors = <&tsens 10>;
834 cpu0_crit: cpu-critical {
840 cpu0_alert: cpu-passive {
847 cooling-maps {
850 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
858 cpu1-thermal {
859 polling-delay-passive = <0>;
860 polling-delay = <0>;
861 thermal-sensors = <&tsens 11>;
864 cpu1_crit: cpu-critical {
870 cpu1_alert: cpu-passive {
877 cooling-maps {
880 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
888 cpu2-thermal {
889 polling-delay-passive = <0>;
890 polling-delay = <0>;
891 thermal-sensors = <&tsens 12>;
894 cpu2_crit: cpu-critical {
900 cpu2_alert: cpu-passive {
907 cooling-maps {
910 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
918 cpu3-thermal {
919 polling-delay-passive = <0>;
920 polling-delay = <0>;
921 thermal-sensors = <&tsens 13>;
924 cpu3_crit: cpu-critical {
930 cpu3_alert: cpu-passive {
937 cooling-maps {
940 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
948 wcss-phyb-thermal {
949 polling-delay-passive = <0>;
950 polling-delay = <0>;
951 thermal-sensors = <&tsens 14>;
954 wcss_phyb-critical {
962 top-glue-thermal {
963 polling-delay-passive = <0>;
964 polling-delay = <0>;
965 thermal-sensors = <&tsens 15>;
968 top_glue-critical {
978 compatible = "arm,armv8-timer";