Lines Matching +full:0 +full:x4aa00000
23 #clock-cells = <0>;
28 #clock-cells = <0>;
34 #size-cells = <0>;
36 CPU0: cpu@0 {
39 reg = <0x0>;
52 reg = <0x1>;
65 reg = <0x2>;
78 reg = <0x3>;
98 qcom,dload-mode = <&tcsr 0x6100>;
105 reg = <0x0 0x40000000 0x0 0x0>;
166 mboxes = <&apcs_glb 0>;
181 reg = <0x0 0x4a100000 0x0 0x400000>;
186 reg = <0x0 0x4a500000 0x0 0x100000>;
191 reg = <0x0 0x4a600000 0x0 0x400000>;
197 reg = <0x0 0x4aa00000 0x0 0x100000>;
203 soc: soc@0 {
207 ranges = <0 0 0 0xffffffff>;
211 reg = <0x00060000 0x6000>;
216 reg = <0x000e3000 0x1000>;
223 reg = <0x000a4000 0x5a1>;
230 reg = <0x00704000 0x20000>;
239 reg = <0x0073a000 0x6000>;
250 reg = <0x004a9000 0x1000>,
251 <0x004a8000 0x1000>;
260 reg = <0x01000000 0x300000>;
264 gpio-ranges = <&tlmm 0 0 65>;
278 reg = <0x01800000 0x80000>;
281 <0>,
282 <0>,
283 <0>,
284 <0>,
285 <0>,
286 <0>;
294 reg = <0x01905000 0x20000>;
300 reg = <0x01937000 0x21000>;
305 reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
322 reg = <0x07884000 0x2b000>;
327 qcom,ee = <0>;
332 reg = <0x078af000 0x200>;
342 reg = <0x078b0000 0x200>;
352 reg = <0x078b1000 0x200>;
362 reg = <0x078b2000 0x200>;
372 reg = <0x078b3000 0x200>;
382 reg = <0x078b4000 0x200>;
392 reg = <0x078b5000 0x600>;
394 #size-cells = <0>;
406 reg = <0x078b6000 0x600>;
408 #size-cells = <0>;
422 reg = <0x078b6000 0x600>;
424 #size-cells = <0>;
436 reg = <0x078b7000 0x600>;
438 #size-cells = <0>;
452 reg = <0x078b7000 0x600>;
454 #size-cells = <0>;
466 reg = <0x078b8000 0x600>;
468 #size-cells = <0>;
482 reg = <0x078b8000 0x600>;
484 #size-cells = <0>;
497 reg = <0x078b9000 0x600>;
499 #size-cells = <0>;
513 reg = <0x078b9000 0x600>;
515 #size-cells = <0>;
527 reg = <0x0007b000 0x180>;
528 #phy-cells = <0>;
541 reg = <0x0007d000 0xa00>;
542 #phy-cells = <0>;
558 #clock-cells = <0>;
566 reg = <0x08af8800 0x400>;
596 reg = <0x8a00000 0xcd00>;
604 snps,hird-threshold = /bits/ 8 <0x0>;
612 reg = <0x0b000000 0x1000>, /* GICD */
613 <0x0b002000 0x2000>, /* GICC */
614 <0x0b001000 0x1000>, /* GICH */
615 <0x0b004000 0x2000>; /* GICV */
621 ranges = <0 0x0b00c000 0x3000>;
623 v2m0: v2m@0 {
625 reg = <0x00000000 0xffd>;
631 reg = <0x00001000 0xffd>;
637 reg = <0x00002000 0xffd>;
644 reg = <0x0b017000 0x1000>;
653 reg = <0x0b111000 0x1000>;
662 reg = <0x0b116000 0x40>;
663 #clock-cells = <0>;
670 reg = <0x0b120000 0x1000>;
676 reg = <0x0b121000 0x1000>,
677 <0x0b122000 0x1000>;
678 frame-number = <0>;
684 reg = <0x0b123000 0x1000>;
691 reg = <0x0b124000 0x1000>;
698 reg = <0x0b125000 0x1000>;
705 reg = <0x0b126000 0x1000>;
712 reg = <0x0b127000 0x1000>;
719 reg = <0x0b128000 0x1000>;
729 polling-delay-passive = <0>;
730 polling-delay = <0>;
742 ubi-0-thermal {
743 polling-delay-passive = <0>;
744 polling-delay = <0>;
757 polling-delay-passive = <0>;
758 polling-delay = <0>;
771 polling-delay-passive = <0>;
772 polling-delay = <0>;
785 polling-delay-passive = <0>;
786 polling-delay = <0>;
799 polling-delay-passive = <0>;
800 polling-delay = <0>;
813 polling-delay-passive = <0>;
814 polling-delay = <0>;
827 polling-delay-passive = <0>;
828 polling-delay = <0>;
857 polling-delay-passive = <0>;
858 polling-delay = <0>;
887 polling-delay-passive = <0>;
888 polling-delay = <0>;
917 polling-delay-passive = <0>;
918 polling-delay = <0>;
947 polling-delay-passive = <0>;
948 polling-delay = <0>;
961 polling-delay-passive = <0>;
962 polling-delay = <0>;