Lines Matching +full:gic +full:- +full:v2m +full:- +full:frame
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
11 #include <dt-bindings/clock/qcom,apss-ipq.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&intc>;
19 sleep_clk: sleep-clk {
20 compatible = "fixed-clock";
21 clock-frequency = <32000>;
22 #clock-cells = <0>;
26 compatible = "fixed-clock";
27 clock-frequency = <24000000>;
28 #clock-cells = <0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
38 compatible = "arm,cortex-a53";
40 enable-method = "psci";
41 next-level-cache = <&L2_0>;
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu_opp_table>;
45 cpu-supply = <&ipq6018_s2>;
50 compatible = "arm,cortex-a53";
51 enable-method = "psci";
53 next-level-cache = <&L2_0>;
55 clock-names = "cpu";
56 operating-points-v2 = <&cpu_opp_table>;
57 cpu-supply = <&ipq6018_s2>;
62 compatible = "arm,cortex-a53";
63 enable-method = "psci";
65 next-level-cache = <&L2_0>;
67 clock-names = "cpu";
68 operating-points-v2 = <&cpu_opp_table>;
69 cpu-supply = <&ipq6018_s2>;
74 compatible = "arm,cortex-a53";
75 enable-method = "psci";
77 next-level-cache = <&L2_0>;
79 clock-names = "cpu";
80 operating-points-v2 = <&cpu_opp_table>;
81 cpu-supply = <&ipq6018_s2>;
84 L2_0: l2-cache {
86 cache-level = <2>;
87 cache-unified;
93 compatible = "qcom,scm-ipq6018", "qcom,scm";
94 qcom,dload-mode = <&tcsr 0x6100>;
98 cpu_opp_table: opp-table-cpu {
99 compatible = "operating-points-v2";
100 opp-shared;
102 opp-864000000 {
103 opp-hz = /bits/ 64 <864000000>;
104 opp-microvolt = <725000>;
105 clock-latency-ns = <200000>;
108 opp-1056000000 {
109 opp-hz = /bits/ 64 <1056000000>;
110 opp-microvolt = <787500>;
111 clock-latency-ns = <200000>;
114 opp-1320000000 {
115 opp-hz = /bits/ 64 <1320000000>;
116 opp-microvolt = <862500>;
117 clock-latency-ns = <200000>;
120 opp-1440000000 {
121 opp-hz = /bits/ 64 <1440000000>;
122 opp-microvolt = <925000>;
123 clock-latency-ns = <200000>;
126 opp-1608000000 {
127 opp-hz = /bits/ 64 <1608000000>;
128 opp-microvolt = <987500>;
129 clock-latency-ns = <200000>;
132 opp-1800000000 {
133 opp-hz = /bits/ 64 <1800000000>;
134 opp-microvolt = <1062500>;
135 clock-latency-ns = <200000>;
140 compatible = "arm,cortex-a53-pmu";
145 compatible = "arm,psci-1.0";
150 compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc";
152 glink-edge {
153 compatible = "qcom,glink-rpm";
155 qcom,rpm-msg-ram = <&rpm_msg_ram>;
158 rpm_requests: rpm-requests {
159 compatible = "qcom,rpm-ipq6018";
160 qcom,glink-channels = "rpm_requests";
163 compatible = "qcom,rpm-mp5496-regulators";
166 regulator-min-microvolt = <725000>;
167 regulator-max-microvolt = <1062500>;
168 regulator-always-on;
175 reserved-memory {
176 #address-cells = <2>;
177 #size-cells = <2>;
182 no-map;
187 no-map;
192 no-map;
197 no-map;
202 no-map;
207 no-map;
213 memory-region = <&smem_region>;
218 #address-cells = <2>;
219 #size-cells = <2>;
221 dma-ranges;
222 compatible = "simple-bus";
225 compatible = "qcom,ipq6018-qusb2-phy";
227 #phy-cells = <0>;
231 clock-names = "cfg_ahb", "ref";
238 compatible = "qcom,ipq6018-qmp-usb3-phy";
240 #address-cells = <2>;
241 #size-cells = <2>;
246 clock-names = "aux", "cfg_ahb", "ref";
250 reset-names = "phy","common";
258 #phy-cells = <0>;
259 #clock-cells = <0>;
261 clock-names = "pipe0";
262 clock-output-names = "gcc_usb0_pipe_clk_src";
267 compatible = "qcom,ipq6018-qusb2-phy";
269 #phy-cells = <0>;
273 clock-names = "cfg_ahb", "ref";
280 compatible = "qcom,ipq6018-qmp-pcie-phy";
283 #address-cells = <2>;
284 #size-cells = <2>;
289 clock-names = "aux", "cfg_ahb";
293 reset-names = "phy",
301 #phy-cells = <0>;
304 clock-names = "pipe0";
305 clock-output-names = "gcc_pcie0_pipe_clk_src";
306 #clock-cells = <0>;
311 #address-cells = <1>;
312 #size-cells = <0>;
313 compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio";
316 clock-names = "gcc_mdio_ahb_clk";
321 compatible = "qcom,ipq6018-qfprom", "qcom,qfprom";
323 #address-cells = <1>;
324 #size-cells = <1>;
328 compatible = "qcom,prng-ee";
331 clock-names = "core";
334 cryptobam: dma-controller@704000 {
335 compatible = "qcom,bam-v1.7.0";
339 clock-names = "bam_clk";
340 #dma-cells = <1>;
342 qcom,controlled-remotely;
346 compatible = "qcom,crypto-v5.1";
351 clock-names = "iface", "bus", "core";
353 dma-names = "rx", "tx";
357 compatible = "qcom,ipq6018-pinctrl";
360 gpio-controller;
361 #gpio-cells = <2>;
362 gpio-ranges = <&tlmm 0 0 80>;
363 interrupt-controller;
364 #interrupt-cells = <2>;
366 serial_3_pins: serial3-state {
369 drive-strength = <8>;
370 bias-pull-down;
373 qpic_pins: qpic-state {
380 drive-strength = <8>;
381 bias-disable;
386 compatible = "qcom,gcc-ipq6018";
389 clock-names = "xo", "sleep_clk";
390 #clock-cells = <1>;
391 #reset-cells = <1>;
395 compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex";
397 #hwlock-cells = <1>;
401 compatible = "qcom,tcsr-ipq6018", "syscon";
406 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
408 #address-cells = <2>;
409 #size-cells = <2>;
414 clock-names = "core",
418 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>,
420 assigned-clock-rates = <133330000>,
430 phy-names = "usb2-phy";
431 tx-fifo-resize;
432 snps,is-utmi-l1-suspend;
433 snps,hird-threshold = /bits/ 8 <0x0>;
440 blsp_dma: dma-controller@7884000 {
441 compatible = "qcom,bam-v1.7.0";
445 clock-names = "bam_clk";
446 #dma-cells = <1>;
451 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
456 clock-names = "core", "iface";
461 compatible = "qcom,spi-qup-v2.2.1";
462 #address-cells = <1>;
463 #size-cells = <0>;
468 clock-names = "core", "iface";
470 dma-names = "tx", "rx";
475 compatible = "qcom,spi-qup-v2.2.1";
476 #address-cells = <1>;
477 #size-cells = <0>;
482 clock-names = "core", "iface";
484 dma-names = "tx", "rx";
489 compatible = "qcom,i2c-qup-v2.2.1";
490 #address-cells = <1>;
491 #size-cells = <0>;
496 clock-names = "core", "iface";
497 clock-frequency = <400000>;
499 dma-names = "tx", "rx";
504 compatible = "qcom,i2c-qup-v2.2.1";
505 #address-cells = <1>;
506 #size-cells = <0>;
511 clock-names = "core", "iface";
512 clock-frequency = <400000>;
514 dma-names = "tx", "rx";
518 qpic_bam: dma-controller@7984000 {
519 compatible = "qcom,bam-v1.7.0";
523 clock-names = "bam_clk";
524 #dma-cells = <1>;
529 qpic_nand: nand-controller@79b0000 {
530 compatible = "qcom,ipq6018-nand";
532 #address-cells = <1>;
533 #size-cells = <0>;
536 clock-names = "core", "aon";
541 dma-names = "tx", "rx", "cmd";
542 pinctrl-0 = <&qpic_pins>;
543 pinctrl-names = "default";
548 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3";
550 #address-cells = <2>;
551 #size-cells = <2>;
558 clock-names = "cfg_noc",
563 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>,
566 assigned-clock-rates = <133330000>,
578 phy-names = "usb2-phy", "usb3-phy";
580 clock-names = "ref";
581 tx-fifo-resize;
582 snps,parkmode-disable-ss-quirk;
583 snps,is-utmi-l1-suspend;
584 snps,hird-threshold = /bits/ 8 <0x0>;
591 intc: interrupt-controller@b000000 {
592 compatible = "qcom,msm-qgic2";
593 #address-cells = <2>;
594 #size-cells = <2>;
595 interrupt-controller;
596 #interrupt-cells = <3>;
604 v2m@0 {
605 compatible = "arm,gic-v2m-frame";
606 msi-controller;
612 compatible = "qcom,kpss-wdt";
616 timeout-sec = <10>;
620 compatible = "qcom,ipq6018-apcs-apps-global";
622 #clock-cells = <1>;
624 clock-names = "pll", "xo";
625 #mbox-cells = <1>;
629 compatible = "qcom,ipq6018-a53pll";
631 #clock-cells = <0>;
633 clock-names = "xo";
637 #address-cells = <1>;
638 #size-cells = <1>;
640 compatible = "arm,armv7-timer-mem";
643 frame@b120000 {
644 frame-number = <0>;
651 frame@b123000 {
652 frame-number = <1>;
658 frame@b124000 {
659 frame-number = <2>;
665 frame@b125000 {
666 frame-number = <3>;
672 frame@b126000 {
673 frame-number = <4>;
679 frame@b127000 {
680 frame-number = <5>;
686 frame@b128000 {
687 frame-number = <6>;
695 compatible = "qcom,ipq6018-wcss-pil";
698 reg-names = "qdsp6",
700 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
705 interrupt-names = "wdog",
709 "stop-ack";
715 reset-names = "wcss_aon_reset",
720 clock-names = "prng";
722 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
724 qcom,smem-states = <&wcss_smp2p_out 0>,
726 qcom,smem-state-names = "shutdown",
729 memory-region = <&q6_region>;
731 glink-edge {
734 qcom,remote-pid = <1>;
738 qcom,glink-channels = "IPCRTR";
744 compatible = "qcom,pcie-ipq6018";
750 reg-names = "dbi", "elbi", "atu", "parf", "config";
753 linux,pci-domain = <0>;
754 bus-range = <0x00 0xff>;
755 num-lanes = <1>;
756 max-link-speed = <3>;
757 #address-cells = <3>;
758 #size-cells = <2>;
761 phy-names = "pciephy";
767 interrupt-names = "msi";
769 #interrupt-cells = <1>;
770 interrupt-map-mask = <0 0 0 0x7>;
771 interrupt-map = <0 0 0 1 &intc 0 0 0 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
781 clock-names = "iface",
795 reset-names = "pipe",
809 compatible = "arm,armv8-timer";
816 wcss: wcss-smp2p {
820 interrupt-parent = <&intc>;
825 qcom,local-pid = <0>;
826 qcom,remote-pid = <1>;
828 wcss_smp2p_out: master-kernel {
829 qcom,entry-name = "master-kernel";
830 #qcom,smem-state-cells = <1>;
833 wcss_smp2p_in: slave-kernel {
834 qcom,entry-name = "slave-kernel";
835 interrupt-controller;
836 #interrupt-cells = <2>;