Lines Matching +full:esc +full:- +full:clock +full:- +full:frequency
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2021-2022 Marek Vasut <marex@denx.de>
10 compatible = "dh,imx8mp-dhcom-som", "fsl,imx8mp";
22 /* Memory size 512 MiB..8 GiB will be filled by U-Boot */
26 reg_eth_vio: regulator-eth-vio {
27 compatible = "regulator-fixed";
29 pinctrl-0 = <&pinctrl_enet_vio>;
30 pinctrl-names = "default";
31 regulator-always-on;
32 regulator-boot-on;
33 regulator-min-microvolt = <3300000>;
34 regulator-max-microvolt = <3300000>;
35 regulator-name = "eth_vio";
36 vin-supply = <&buck4>;
39 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
40 compatible = "regulator-fixed";
41 enable-active-high;
43 off-on-delay-us = <12000>;
44 pinctrl-names = "default";
45 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
46 regulator-max-microvolt = <3300000>;
47 regulator-min-microvolt = <3300000>;
48 regulator-name = "VDD_3V3_SD";
49 startup-delay-us = <100>;
50 vin-supply = <&buck4>;
53 reg_vdd_3p3v_awo: regulator-vdd-3p3v-awo { /* VDD_3V3_AWO */
54 compatible = "regulator-fixed";
55 regulator-always-on;
56 regulator-min-microvolt = <3300000>;
57 regulator-max-microvolt = <3300000>;
58 regulator-name = "VDD_3P3V_AWO";
63 cpu-supply = <&buck2>;
67 cpu-supply = <&buck2>;
71 cpu-supply = <&buck2>;
75 cpu-supply = <&buck2>;
79 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_ecspi1>;
81 cs-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_ecspi2>;
88 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_eqos_rgmii>;
95 phy-handle = <ðphy0g>;
96 phy-mode = "rgmii-id";
100 compatible = "snps,dwmac-mdio";
101 #address-cells = <1>;
102 #size-cells = <0>;
105 ethphy0f: ethernet-phy@0 { /* SMSC LAN8740Ai */
106 compatible = "ethernet-phy-id0007.c110",
107 "ethernet-phy-ieee802.3-c22";
108 interrupt-parent = <&gpio3>;
110 pinctrl-0 = <&pinctrl_ethphy0>;
111 pinctrl-names = "default";
113 reset-assert-us = <1000>;
114 reset-deassert-us = <1000>;
115 reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
116 /* Non-default PHY population option. */
120 ethphy0g: ethernet-phy@5 { /* Micrel KSZ9131RNXI */
121 compatible = "ethernet-phy-id0022.1642",
122 "ethernet-phy-ieee802.3-c22";
123 interrupt-parent = <&gpio3>;
125 micrel,led-mode = <0>;
126 pinctrl-0 = <&pinctrl_ethphy0>;
127 pinctrl-names = "default";
129 reset-assert-us = <1000>;
130 reset-deassert-us = <1000>;
131 reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_fec_rmii>;
141 phy-handle = <ðphy1f>;
142 phy-mode = "rmii";
143 fsl,magic-packet;
147 #address-cells = <1>;
148 #size-cells = <0>;
151 ethphy1f: ethernet-phy@1 { /* SMSC LAN8740Ai */
152 compatible = "ethernet-phy-id0007.c110",
153 "ethernet-phy-ieee802.3-c22";
154 interrupt-parent = <&gpio4>;
156 pinctrl-0 = <&pinctrl_ethphy1>;
157 pinctrl-names = "default";
159 reset-assert-us = <1000>;
160 reset-deassert-us = <1000>;
161 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
162 /* Non-default PHY population option. */
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_flexcan1>;
175 pinctrl-names = "default";
176 pinctrl-0 = <&pinctrl_flexcan2>;
181 pinctrl-names = "default";
182 pinctrl-0 = <&pinctrl_flexspi>;
186 compatible = "jedec,spi-nor";
188 spi-max-frequency = <80000000>;
189 spi-tx-bus-width = <4>;
190 spi-rx-bus-width = <4>;
195 gpio-line-names =
196 "DHCOM-G", "", "", "", "", "DHCOM-I", "DHCOM-J", "DHCOM-L",
197 "DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
203 gpio-line-names =
205 "", "", "", "DHCOM-K", "", "", "", "",
206 "", "", "", "", "DHCOM-INT", "", "", "",
211 gpio-line-names =
213 "", "", "", "", "", "", "SOM-HW0", "",
214 "", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
215 "SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
219 gpio-line-names =
222 "", "", "", "SOM-HW1", "", "", "", "",
223 "", "", "", "DHCOM-D", "", "", "", "";
227 gpio-line-names =
228 "", "", "DHCOM-C", "", "", "", "", "",
230 "", "", "", "", "", "", "DHCOM-E", "DHCOM-F",
235 clock-frequency = <100000>;
236 pinctrl-names = "default", "gpio";
237 pinctrl-0 = <&pinctrl_i2c3>;
238 pinctrl-1 = <&pinctrl_i2c3_gpio>;
239 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
240 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
245 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_tc9595>;
248 clock-names = "ref";
250 assigned-clocks = <&clk IMX8MP_CLK_CLKOUT2_SEL>,
253 assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>;
254 assigned-clock-rates = <13000000>, <13000000>, <208000000>;
255 reset-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
259 #address-cells = <1>;
260 #size-cells = <0>;
266 data-lanes = <1 2 3 4>;
267 remote-endpoint = <&dsi_out>;
276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_pmic>;
278 interrupt-parent = <&gpio1>;
287 buck1: BUCK1 { /* VDD_SOC (dual-phase with BUCK3) */
288 regulator-min-microvolt = <850000>;
289 regulator-max-microvolt = <1000000>;
290 regulator-ramp-delay = <3125>;
291 regulator-always-on;
292 regulator-boot-on;
296 regulator-min-microvolt = <850000>;
297 regulator-max-microvolt = <1000000>;
298 regulator-ramp-delay = <3125>;
299 regulator-always-on;
300 regulator-boot-on;
304 regulator-min-microvolt = <3300000>;
305 regulator-max-microvolt = <3300000>;
306 regulator-always-on;
307 regulator-boot-on;
311 regulator-min-microvolt = <1800000>;
312 regulator-max-microvolt = <1800000>;
313 regulator-always-on;
314 regulator-boot-on;
318 regulator-min-microvolt = <1100000>;
319 regulator-max-microvolt = <1100000>;
320 regulator-always-on;
321 regulator-boot-on;
325 regulator-min-microvolt = <1800000>;
326 regulator-max-microvolt = <1800000>;
327 regulator-always-on;
328 regulator-boot-on;
332 regulator-min-microvolt = <1800000>;
333 regulator-max-microvolt = <1800000>;
334 regulator-always-on;
335 regulator-boot-on;
339 regulator-min-microvolt = <3300000>;
340 regulator-max-microvolt = <3300000>;
344 regulator-min-microvolt = <1800000>;
345 regulator-max-microvolt = <3300000>;
353 #address-cells = <1>;
354 #size-cells = <0>;
392 interrupts-extended = <&gpio4 0 IRQ_TYPE_EDGE_FALLING>;
393 pinctrl-names = "default";
394 pinctrl-0 = <&pinctrl_touch>;
395 vio-supply = <&buck4>;
407 interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>;
408 pinctrl-names = "default";
409 pinctrl-0 = <&pinctrl_rtc>;
420 clock-frequency = <100000>;
421 pinctrl-names = "default", "gpio";
422 pinctrl-0 = <&pinctrl_i2c4>;
423 pinctrl-1 = <&pinctrl_i2c4_gpio>;
424 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
425 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
430 clock-frequency = <100000>;
431 pinctrl-names = "default", "gpio";
432 pinctrl-0 = <&pinctrl_i2c5>;
433 pinctrl-1 = <&pinctrl_i2c5_gpio>;
434 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
435 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
440 samsung,burst-clock-frequency = <160000000>;
441 samsung,esc-clock-frequency = <10000000>;
448 data-lanes = <1 2 3 4>;
449 remote-endpoint = <&tc_bridge_in>;
456 pinctrl-0 = <&pinctrl_pwm1>;
457 pinctrl-names = "default";
463 pinctrl-names = "default";
464 pinctrl-0 = <&pinctrl_uart1>;
470 pinctrl-names = "default";
471 pinctrl-0 = <&pinctrl_uart2>;
472 uart-has-rtscts;
476 * PLL1 at 80 MHz supplies UART2 root with 80 MHz clock,
482 assigned-clocks = <&clk IMX8MP_CLK_UART2>;
483 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
484 assigned-clock-rates = <80000000>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&pinctrl_uart2_bt>;
489 compatible = "cypress,cyw4373a0-bt";
490 shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
491 max-speed = <4000000>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&pinctrl_uart3>;
498 uart-has-rtscts;
503 pinctrl-names = "default";
504 pinctrl-0 = <&pinctrl_uart4>;
517 pinctrl-names = "default";
518 pinctrl-0 = <&pinctrl_usb0_vbus>;
532 pinctrl-names = "default";
533 pinctrl-0 = <&pinctrl_usb1_vbus>;
540 pinctrl-names = "default", "state_100mhz", "state_200mhz";
541 pinctrl-0 = <&pinctrl_usdhc1>;
542 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
543 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
544 vmmc-supply = <&buck4>;
545 bus-width = <4>;
546 non-removable;
547 cap-power-off-card;
548 keep-power-in-suspend;
551 #address-cells = <1>;
552 #size-cells = <0>;
556 compatible = "cypress,cyw4373-fmac", "brcm,bcm4329-fmac";
558 * The "host-wake" interrupt output is by default not
562 reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
568 pinctrl-names = "default", "state_100mhz", "state_200mhz";
569 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
570 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
571 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
572 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
573 vmmc-supply = <®_usdhc2_vmmc>;
574 bus-width = <4>;
580 pinctrl-names = "default", "state_100mhz", "state_200mhz";
581 pinctrl-0 = <&pinctrl_usdhc3>;
582 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
583 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
584 vmmc-supply = <&buck4>;
585 vqmmc-supply = <&buck5>;
586 bus-width = <8>;
587 non-removable;
592 pinctrl-names = "default";
593 pinctrl-0 = <&pinctrl_wdog>;
594 fsl,ext-reset-output;
599 pinctrl-0 = <&pinctrl_hog_base
606 pinctrl-names = "default";
608 pinctrl_dhcom_a: dhcom-a-grp {
610 /* ENET_QOS_EVENT0-OUT */
615 pinctrl_dhcom_b: dhcom-b-grp {
617 /* ENET_QOS_EVENT0-IN */
622 pinctrl_dhcom_c: dhcom-c-grp {
629 pinctrl_dhcom_d: dhcom-d-grp {
636 pinctrl_dhcom_e: dhcom-e-grp {
643 pinctrl_dhcom_f: dhcom-f-grp {
650 pinctrl_dhcom_g: dhcom-g-grp {
657 pinctrl_dhcom_h: dhcom-h-grp {
664 pinctrl_dhcom_i: dhcom-i-grp {
671 pinctrl_dhcom_j: dhcom-j-grp {
678 pinctrl_dhcom_k: dhcom-k-grp {
685 pinctrl_dhcom_l: dhcom-l-grp {
692 pinctrl_dhcom_int: dhcom-int-grp {
699 pinctrl_hog_base: dhcom-hog-base-grp {
712 pinctrl_ecspi1: dhcom-ecspi1-grp {
721 pinctrl_ecspi2: dhcom-ecspi2-grp {
730 pinctrl_eqos_rgmii: dhcom-eqos-rgmii-grp { /* RGMII */
749 pinctrl_eqos_rmii: dhcom-eqos-rmii-grp { /* RMII */
760 /* Clock */
765 pinctrl_enet_vio: dhcom-enet-vio-grp {
771 pinctrl_ethphy0: dhcom-ethphy0-grp {
780 pinctrl_ethphy1: dhcom-ethphy1-grp {
789 pinctrl_fec_rgmii: dhcom-fec-rgmii-grp { /* RGMII */
810 pinctrl_fec_rmii: dhcom-fec-rmii-grp { /* RMII */
821 /* Clock */
826 pinctrl_flexcan1: dhcom-flexcan1-grp {
833 pinctrl_flexcan2: dhcom-flexcan2-grp {
840 pinctrl_flexspi: dhcom-flexspi-grp {
851 pinctrl_hdmi: dhcom-hdmi-grp {
858 pinctrl_i2c3: dhcom-i2c3-grp {
865 pinctrl_i2c3_gpio: dhcom-i2c3-gpio-grp {
872 pinctrl_i2c4: dhcom-i2c4-grp {
879 pinctrl_i2c4_gpio: dhcom-i2c4-gpio-grp {
886 pinctrl_i2c5: dhcom-i2c5-grp {
893 pinctrl_i2c5_gpio: dhcom-i2c5-gpio-grp {
900 pinctrl_pmic: dhcom-pmic-grp {
907 pinctrl_pwm1: dhcom-pwm1-grp {
913 pinctrl_rtc: dhcom-rtc-grp {
920 pinctrl_tc9595: dhcom-tc9595-grp {
924 /* DSI-CONV_INT Interrupt */
929 pinctrl_sai3: dhcom-sai3-grp {
938 pinctrl_touch: dhcom-touch-grp {
945 pinctrl_uart1: dhcom-uart1-grp {
955 pinctrl_uart2: dhcom-uart2-grp {
965 pinctrl_uart2_bt: dhcom-uart2-bt-grp {
972 pinctrl_uart3: dhcom-uart3-grp {
981 pinctrl_uart4: dhcom-uart4-grp {
988 pinctrl_usb0_vbus: dhcom-usb0-grp {
994 pinctrl_usb1_vbus: dhcom-usb1-grp {
1001 pinctrl_usdhc1: dhcom-usdhc1-grp {
1014 pinctrl_usdhc1_100mhz: dhcom-usdhc1-100mhz-grp {
1027 pinctrl_usdhc1_200mhz: dhcom-usdhc1-200mhz-grp {
1040 pinctrl_usdhc2: dhcom-usdhc2-grp {
1052 pinctrl_usdhc2_100mhz: dhcom-usdhc2-100mhz-grp {
1064 pinctrl_usdhc2_200mhz: dhcom-usdhc2-200mhz-grp {
1076 pinctrl_usdhc2_vmmc: dhcom-usdhc2-vmmc-grp {
1082 pinctrl_usdhc2_gpio: dhcom-usdhc2-gpio-grp {
1088 pinctrl_usdhc3: dhcom-usdhc3-grp {
1105 pinctrl_usdhc3_100mhz: dhcom-usdhc3-100mhz-grp {
1122 pinctrl_usdhc3_200mhz: dhcom-usdhc3-200mhz-grp {
1139 pinctrl_wdog: dhcom-wdog-grp {