Lines Matching +full:0 +full:x306a0000
46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
68 i-cache-size = <0x8000>;
71 d-cache-size = <0x8000>;
85 reg = <0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
104 reg = <0x2>;
108 i-cache-size = <0x8000>;
111 d-cache-size = <0x8000>;
123 reg = <0x3>;
127 i-cache-size = <0x8000>;
130 d-cache-size = <0x8000>;
143 cache-size = <0x80000>;
156 opp-supported-hw = <0xb00>, <0x7>;
164 opp-supported-hw = <0x300>, <0x7>;
172 opp-supported-hw = <0x100>, <0x3>;
180 #clock-cells = <0>;
187 #clock-cells = <0>;
194 #clock-cells = <0>;
201 #clock-cells = <0>;
208 #clock-cells = <0>;
215 #clock-cells = <0>;
273 soc: soc@0 {
277 ranges = <0x0 0x0 0x0 0x3e000000>;
278 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
284 reg = <0x30000000 0x400000>;
293 reg = <0x30000000 0x100000>;
298 reg = <0x30020000 0x10000>;
299 #sound-dai-cells = <0>;
306 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
313 reg = <0x30030000 0x10000>;
314 #sound-dai-cells = <0>;
321 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
328 reg = <0x30050000 0x10000>;
329 #sound-dai-cells = <0>;
336 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
339 fsl,dataline = <0 0xf 0xf>;
345 reg = <0x30060000 0x10000>;
346 #sound-dai-cells = <0>;
353 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
360 reg = <0x30080000 0x10000>;
372 dmas = <&sdma2 24 25 0x80000000>;
374 #sound-dai-cells = <0>;
380 reg = <0x30090000 0x10000>;
397 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
404 reg = <0x300b0000 0x10000>;
405 #sound-dai-cells = <0>;
412 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
419 reg = <0x300c0000 0x10000>;
423 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
424 <&sdma2 18 23 0> , <&sdma2 19 23 0>,
425 <&sdma2 20 23 0> , <&sdma2 21 23 0>,
426 <&sdma2 22 23 0> , <&sdma2 23 23 0>;
440 reg = <0x30200000 0x10000>;
448 gpio-ranges = <&iomuxc 0 10 30>;
453 reg = <0x30210000 0x10000>;
461 gpio-ranges = <&iomuxc 0 40 21>;
466 reg = <0x30220000 0x10000>;
474 gpio-ranges = <&iomuxc 0 61 26>;
479 reg = <0x30230000 0x10000>;
492 reg = <0x30240000 0x10000>;
500 gpio-ranges = <&iomuxc 0 119 30>;
505 reg = <0x30260000 0x10000>;
509 #thermal-sensor-cells = <0>;
514 reg = <0x30280000 0x10000>;
522 reg = <0x30290000 0x10000>;
530 reg = <0x302a0000 0x10000>;
538 reg = <0x302b0000 0x10000>;
549 reg = <0x302c0000 0x10000>;
560 reg = <0x30330000 0x10000>;
565 reg = <0x30340000 0x10000>;
570 reg = <0x30350000 0x10000>;
581 * Fuse Address = (ADDR * 4) + 0x400
584 * +0x10 in Fusemap Description Table (e.g.
585 * reg = <0x4 0x8> describes fuses 0x410 and
586 * 0x420).
588 imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
589 reg = <0x4 0x8>;
592 cpu_speed_grade: speed-grade@10 { /* 0x440 */
593 reg = <0x10 4>;
596 tmu_calib: calib@3c { /* 0x4f0 */
597 reg = <0x3c 4>;
600 fec_mac_address: mac-address@90 { /* 0x640 */
601 reg = <0x90 6>;
607 reg = <0x30360000 0x10000>;
612 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
613 reg = <0x30370000 0x10000>;
616 compatible = "fsl,sec-v4.0-mon-rtc-lp";
618 offset = <0x34>;
626 compatible = "fsl,sec-v4.0-pwrkey";
639 reg = <0x30380000 0x10000>;
657 assigned-clock-rates = <0>, <0>, <0>,
667 reg = <0x30390000 0x10000>;
674 reg = <0x303a0000 0x10000>;
680 #size-cells = <0>;
682 pgc_hsiomix: power-domain@0 {
683 #power-domain-cells = <0>;
689 #power-domain-cells = <0>;
694 #power-domain-cells = <0>;
703 #power-domain-cells = <0>;
710 #power-domain-cells = <0>;
720 reg = <0x30400000 0x400000>;
727 reg = <0x30660000 0x10000>;
738 reg = <0x30670000 0x10000>;
749 reg = <0x30680000 0x10000>;
760 reg = <0x30690000 0x10000>;
771 reg = <0x306a0000 0x20000>;
780 reg = <0x30800000 0x400000>;
789 reg = <0x30800000 0x100000>;
795 #size-cells = <0>;
796 reg = <0x30820000 0x10000>;
801 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
809 #size-cells = <0>;
810 reg = <0x30830000 0x10000>;
823 #size-cells = <0>;
824 reg = <0x30840000 0x10000>;
836 reg = <0x30860000 0x10000>;
841 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
848 reg = <0x30880000 0x10000>;
853 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
860 reg = <0x30890000 0x10000>;
870 compatible = "fsl,sec-v4.0";
873 reg = <0x30900000 0x40000>;
874 ranges = <0 0x30900000 0x40000>;
881 compatible = "fsl,sec-v4.0-job-ring";
882 reg = <0x1000 0x1000>;
888 compatible = "fsl,sec-v4.0-job-ring";
889 reg = <0x2000 0x1000>;
894 compatible = "fsl,sec-v4.0-job-ring";
895 reg = <0x3000 0x1000>;
903 #size-cells = <0>;
904 reg = <0x30a20000 0x10000>;
913 #size-cells = <0>;
914 reg = <0x30a30000 0x10000>;
922 #size-cells = <0>;
924 reg = <0x30a40000 0x10000>;
933 #size-cells = <0>;
934 reg = <0x30a50000 0x10000>;
942 reg = <0x30a60000 0x10000>;
947 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
954 reg = <0x30aa0000 0x10000>;
962 reg = <0x30b40000 0x10000>;
976 reg = <0x30b50000 0x10000>;
990 reg = <0x30b60000 0x10000>;
1004 #size-cells = <0>;
1006 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1017 reg = <0x30bd0000 0x10000>;
1028 reg = <0x30be0000 0x10000>;
1048 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1053 fsl,stop-mode = <&gpr 0x10 3>;
1061 reg = <0x32c00000 0x400000>;
1068 reg = <0x32e00000 0x10000>;
1086 reg = <0x32e10000 0x400>;
1096 #size-cells = <0>;
1098 port@0 {
1099 reg = <0>;
1110 reg = <0x32e20000 0x8000>;
1121 #size-cells = <0>;
1123 port@0 {
1124 reg = <0>;
1134 reg = <0x32e28000 0x100>;
1177 reg = <0x32e30000 0x1000>;
1193 #size-cells = <0>;
1195 port@0 {
1196 reg = <0>;
1211 reg = <0x32e40000 0x200>;
1218 fsl,usbmisc = <&usbmisc1 0>;
1227 reg = <0x32e40200 0x200>;
1233 reg = <0x33000000 0x2000>;
1246 #size-cells = <0>;
1247 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1254 dmas = <&dma_apbh 0>;
1261 reg = <0x38000000 0x8000>;
1287 reg = <0x38800000 0x10000>,
1288 <0x38880000 0xc0000>;
1296 reg = <0x3d400000 0x400000>;
1306 reg = <0x3d800000 0x400000>;
1312 #phy-cells = <0>;