Lines Matching +full:2 +full:c010000
18 #address-cells = <2>;
19 #size-cells = <2>;
39 #cooling-cells = <2>;
56 #cooling-cells = <2>;
61 cache-level = <2>;
124 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
126 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
130 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
141 #address-cells = <2>;
142 #size-cells = <2>;
210 #address-cells = <2>;
211 #size-cells = <2>;
267 #clock-cells = <2>;
380 QORIQ_CLK_PLL_DIV(2)>;
396 QORIQ_CLK_PLL_DIV(2)>;
412 QORIQ_CLK_PLL_DIV(2)>;
413 dmas = <&edma0 0 54>, <&edma0 0 2>;
452 QORIQ_CLK_PLL_DIV(2)>,
454 QORIQ_CLK_PLL_DIV(2)>;
464 QORIQ_CLK_PLL_DIV(2)>,
466 QORIQ_CLK_PLL_DIV(2)>;
476 QORIQ_CLK_PLL_DIV(2)>;
485 QORIQ_CLK_PLL_DIV(2)>;
495 QORIQ_CLK_PLL_DIV(2)>;
508 QORIQ_CLK_PLL_DIV(2)>;
521 QORIQ_CLK_PLL_DIV(2)>;
534 QORIQ_CLK_PLL_DIV(2)>;
547 QORIQ_CLK_PLL_DIV(2)>;
560 QORIQ_CLK_PLL_DIV(2)>;
569 #dma-cells = <2>;
580 QORIQ_CLK_PLL_DIV(2)>,
582 QORIQ_CLK_PLL_DIV(2)>;
590 #gpio-cells = <2>;
592 #interrupt-cells = <2>;
601 #gpio-cells = <2>;
603 #interrupt-cells = <2>;
612 #gpio-cells = <2>;
614 #interrupt-cells = <2>;
645 QORIQ_CLK_PLL_DIV(2)>;
658 #size-cells = <2>;
669 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
697 #size-cells = <2>;
708 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
834 fsl,dma-queues = <2>;
849 cluster1_core1_watchdog: watchdog@c010000 {
866 <&clockgen QORIQ_CLK_HWACCEL 2>,
867 <&clockgen QORIQ_CLK_HWACCEL 2>,
868 <&clockgen QORIQ_CLK_HWACCEL 2>;
884 clocks = <&clockgen QORIQ_CLK_HWACCEL 2>,
885 <&clockgen QORIQ_CLK_HWACCEL 2>,
886 <&clockgen QORIQ_CLK_HWACCEL 2>;
888 #cooling-cells = <2>;
897 QORIQ_CLK_PLL_DIV(2)>,
899 QORIQ_CLK_PLL_DIV(2)>,
901 QORIQ_CLK_PLL_DIV(2)>,
903 QORIQ_CLK_PLL_DIV(2)>;
918 QORIQ_CLK_PLL_DIV(2)>,
920 QORIQ_CLK_PLL_DIV(2)>,
922 QORIQ_CLK_PLL_DIV(2)>,
924 QORIQ_CLK_PLL_DIV(2)>;
939 QORIQ_CLK_PLL_DIV(2)>,
941 QORIQ_CLK_PLL_DIV(2)>,
943 QORIQ_CLK_PLL_DIV(2)>,
945 QORIQ_CLK_PLL_DIV(2)>;
960 QORIQ_CLK_PLL_DIV(2)>,
962 QORIQ_CLK_PLL_DIV(2)>,
964 QORIQ_CLK_PLL_DIV(2)>,
966 QORIQ_CLK_PLL_DIV(2)>;
981 QORIQ_CLK_PLL_DIV(2)>,
983 QORIQ_CLK_PLL_DIV(2)>,
985 QORIQ_CLK_PLL_DIV(2)>,
987 QORIQ_CLK_PLL_DIV(2)>;
1002 QORIQ_CLK_PLL_DIV(2)>,
1004 QORIQ_CLK_PLL_DIV(2)>,
1006 QORIQ_CLK_PLL_DIV(2)>,
1008 QORIQ_CLK_PLL_DIV(2)>;
1080 #size-cells = <2>;
1114 enetc_port2: ethernet@0,2 {
1163 mscc_felix_port2: port@2 {
1164 reg = <2>;