1 // SPDX-License-Identifier: GPL-2.0-only
3  * OMAP4 CM instance functions
6  * Copyright (C) 2008-2011 Texas Instruments, Inc.
11  * or CM2 hardware modules.  For example, the EMU_CM CM instance is in
12  * the PRM hardware module.  What a mess...
26 #include "cm-regbits-34xx.h"
30 #include "prcm-common.h"
42  *   0x0 func:     Module is fully functional, including OCP
43  *   0x1 trans:    Module is performing transition: wakeup, or sleep, or sleep
45  *   0x2 idle:     Module is in Idle mode (only OCP part). It is functional if
47  *   0x3 disabled: Module is disabled and cannot be accessed
58  * omap_cm_base_init - Populates the cm partitions
61  * array used for read/write of cm module registers.
77  * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
79  * @inst: CM instance register offset (*_INST macro)
80  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
94  * _is_module_ready - can module registers be accessed without causing an abort?
96  * @inst: CM instance register offset (*_INST macro)
97  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
99  * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
112 /* Read a register in a CM instance */
121 /* Write into a register in a CM instance */
130 /* Read-modify-write a register in CM1. Caller must lock */
171  * _clktrctrl_write - write @c to a CM_CLKSTCTRL.CLKTRCTRL register bitfield
174  * @inst: CM instance register offset (*_INST macro)
177  * @c must be the unshifted value for CLKTRCTRL - i.e., this function
191  * omap4_cminst_is_clkdm_in_hwsup - is a clockdomain in hwsup idle mode?
193  * @inst: CM instance register offset (*_INST macro)
197  * is in hardware-supervised idle mode, or 0 otherwise.
211  * omap4_cminst_clkdm_enable_hwsup - put a clockdomain in hwsup-idle mode
213  * @inst: CM instance register offset (*_INST macro)
217  * hardware-supervised idle mode.  No return value.
225  * omap4_cminst_clkdm_disable_hwsup - put a clockdomain in swsup-idle mode
227  * @inst: CM instance register offset (*_INST macro)
231  * software-supervised idle mode, i.e., controlled manually by the
240  * omap4_cminst_clkdm_force_sleep - try to take a clockdomain out of idle
242  * @inst: CM instance register offset (*_INST macro)
263  * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state
265  * @inst: CM instance register offset (*_INST macro)
266  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
269  * Wait for the module IDLEST to be functional. If the idle state is in any
270  * the non functional state (trans, idle or disabled), module and thus the
282 	return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;  in omap4_cminst_wait_module_ready()
286  * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled'
289  * @inst: CM instance register offset (*_INST macro)
290  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
293  * Wait for the module IDLEST to be disabled. Some PRCM transition,
294  * like reset assertion or parent clock de-activation must wait the
295  * module to be fully disabled.
306 	return (i < MAX_MODULE_DISABLE_TIME) ? 0 : -EBUSY;  in omap4_cminst_wait_module_idle()
310  * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL
311  * @mode: Module mode (SW or HW)
313  * @inst: CM instance register offset (*_INST macro)
314  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
330  * omap4_cminst_module_disable - Disable the module inside CLKCTRL
332  * @inst: CM instance register offset (*_INST macro)
333  * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
347  * Clockdomain low-level functions
353 	omap4_cminst_set_inst_reg_bits((1 << clkdm2->dep_bit),  in omap4_clkdm_add_wkup_sleep_dep()
354 				       clkdm1->prcm_partition,  in omap4_clkdm_add_wkup_sleep_dep()
355 				       clkdm1->cm_inst, clkdm1->clkdm_offs +  in omap4_clkdm_add_wkup_sleep_dep()
363 	omap4_cminst_clear_inst_reg_bits((1 << clkdm2->dep_bit),  in omap4_clkdm_del_wkup_sleep_dep()
364 					 clkdm1->prcm_partition,  in omap4_clkdm_del_wkup_sleep_dep()
365 					 clkdm1->cm_inst, clkdm1->clkdm_offs +  in omap4_clkdm_del_wkup_sleep_dep()
373 	return omap4_cminst_read_inst_reg_bits(clkdm1->prcm_partition,  in omap4_clkdm_read_wkup_sleep_dep()
374 					       clkdm1->cm_inst,  in omap4_clkdm_read_wkup_sleep_dep()
375 					       clkdm1->clkdm_offs +  in omap4_clkdm_read_wkup_sleep_dep()
377 					       (1 << clkdm2->dep_bit));  in omap4_clkdm_read_wkup_sleep_dep()
385 	if (!clkdm->prcm_partition)  in omap4_clkdm_clear_all_wkup_sleep_deps()
388 	for (cd = clkdm->wkdep_srcs; cd && cd->clkdm_name; cd++) {  in omap4_clkdm_clear_all_wkup_sleep_deps()
389 		if (!cd->clkdm)  in omap4_clkdm_clear_all_wkup_sleep_deps()
392 		mask |= 1 << cd->clkdm->dep_bit;  in omap4_clkdm_clear_all_wkup_sleep_deps()
393 		cd->wkdep_usecount = 0;  in omap4_clkdm_clear_all_wkup_sleep_deps()
396 	omap4_cminst_clear_inst_reg_bits(mask, clkdm->prcm_partition,  in omap4_clkdm_clear_all_wkup_sleep_deps()
397 					 clkdm->cm_inst, clkdm->clkdm_offs +  in omap4_clkdm_clear_all_wkup_sleep_deps()
404 	if (clkdm->flags & CLKDM_CAN_HWSUP)  in omap4_clkdm_sleep()
405 		omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,  in omap4_clkdm_sleep()
406 						clkdm->cm_inst,  in omap4_clkdm_sleep()
407 						clkdm->clkdm_offs);  in omap4_clkdm_sleep()
408 	else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)  in omap4_clkdm_sleep()
409 		omap4_cminst_clkdm_force_sleep(clkdm->prcm_partition,  in omap4_clkdm_sleep()
410 					       clkdm->cm_inst,  in omap4_clkdm_sleep()
411 					       clkdm->clkdm_offs);  in omap4_clkdm_sleep()
413 		return -EINVAL;  in omap4_clkdm_sleep()
420 	omap4_cminst_clkdm_force_wakeup(clkdm->prcm_partition,  in omap4_clkdm_wakeup()
421 					clkdm->cm_inst, clkdm->clkdm_offs);  in omap4_clkdm_wakeup()
427 	omap4_cminst_clkdm_enable_hwsup(clkdm->prcm_partition,  in omap4_clkdm_allow_idle()
428 					clkdm->cm_inst, clkdm->clkdm_offs);  in omap4_clkdm_allow_idle()
433 	if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)  in omap4_clkdm_deny_idle()
436 		omap4_cminst_clkdm_disable_hwsup(clkdm->prcm_partition,  in omap4_clkdm_deny_idle()
437 						 clkdm->cm_inst,  in omap4_clkdm_deny_idle()
438 						 clkdm->clkdm_offs);  in omap4_clkdm_deny_idle()
443 	if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)  in omap4_clkdm_clk_enable()
453 	if (!clkdm->prcm_partition)  in omap4_clkdm_clk_disable()
461 	if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&  in omap4_clkdm_clk_disable()
462 	    !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {  in omap4_clkdm_clk_disable()
467 	hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,  in omap4_clkdm_clk_disable()
468 					clkdm->cm_inst, clkdm->clkdm_offs);  in omap4_clkdm_clk_disable()
470 	if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))  in omap4_clkdm_clk_disable()
482  * omap4_clkdm_save_context - Save the clockdomain modulemode context
489 	clkdm->context = omap4_cminst_read_inst_reg(clkdm->prcm_partition,  in omap4_clkdm_save_context()
490 						    clkdm->cm_inst,  in omap4_clkdm_save_context()
491 						    clkdm->clkdm_offs +  in omap4_clkdm_save_context()
493 	clkdm->context &= OMAP4430_MODULEMODE_MASK;  in omap4_clkdm_save_context()
498  * omap4_clkdm_restore_context - Restore the clockdomain modulemode context
505 	switch (clkdm->context) {  in omap4_clkdm_restore_context()