Lines Matching +full:non +full:- +full:default
1 # SPDX-License-Identifier: GPL-2.0
4 default y
150 The ARM series is a line of low-power-consumption RISC chip designs
152 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
153 manufactured, but legacy ARM-based PC hardware remains popular in
164 supported in LLD until version 14. The combined range is -/+ 256 MiB,
177 default 8
179 DMA mapping framework by default aligns all buffers to the smallest
211 default y
215 default y
231 default y
235 default y
254 default y
257 Patch phys-to-virt and virt-to-phys translation functions at
261 This can only be used with non-XIP MMU kernels where the base
285 default DRAM_BASE if !MMU
286 default 0x00000000 if ARCH_FOOTBRIDGE
287 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
288 default 0xa0000000 if ARCH_PXA
289 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
290 default 0
301 default 3 if ARM_LPAE
302 default 2
307 bool "MMU-based Paged Memory Management Support"
308 default y
310 Select if you want MMU-based virtualised addressing space
320 default 8
323 default 14 if PAGE_OFFSET=0x40000000
324 default 15 if PAGE_OFFSET=0x80000000
325 default 16
330 default y
350 # https://github.com/llvm/llvm-project/issues/50764
358 # https://github.com/llvm/llvm-project/issues/50764
382 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
383 default y
421 # This is sorted alphabetically by mach-* pathname. However, plat-*
423 # plat- suffix) or along side the corresponding mach-* source.
425 source "arch/arm/mach-actions/Kconfig"
427 source "arch/arm/mach-alpine/Kconfig"
429 source "arch/arm/mach-artpec/Kconfig"
431 source "arch/arm/mach-asm9260/Kconfig"
433 source "arch/arm/mach-aspeed/Kconfig"
435 source "arch/arm/mach-at91/Kconfig"
437 source "arch/arm/mach-axxia/Kconfig"
439 source "arch/arm/mach-bcm/Kconfig"
441 source "arch/arm/mach-berlin/Kconfig"
443 source "arch/arm/mach-clps711x/Kconfig"
445 source "arch/arm/mach-davinci/Kconfig"
447 source "arch/arm/mach-digicolor/Kconfig"
449 source "arch/arm/mach-dove/Kconfig"
451 source "arch/arm/mach-ep93xx/Kconfig"
453 source "arch/arm/mach-exynos/Kconfig"
455 source "arch/arm/mach-footbridge/Kconfig"
457 source "arch/arm/mach-gemini/Kconfig"
459 source "arch/arm/mach-highbank/Kconfig"
461 source "arch/arm/mach-hisi/Kconfig"
463 source "arch/arm/mach-hpe/Kconfig"
465 source "arch/arm/mach-imx/Kconfig"
467 source "arch/arm/mach-ixp4xx/Kconfig"
469 source "arch/arm/mach-keystone/Kconfig"
471 source "arch/arm/mach-lpc32xx/Kconfig"
473 source "arch/arm/mach-mediatek/Kconfig"
475 source "arch/arm/mach-meson/Kconfig"
477 source "arch/arm/mach-milbeaut/Kconfig"
479 source "arch/arm/mach-mmp/Kconfig"
481 source "arch/arm/mach-moxart/Kconfig"
483 source "arch/arm/mach-mstar/Kconfig"
485 source "arch/arm/mach-mv78xx0/Kconfig"
487 source "arch/arm/mach-mvebu/Kconfig"
489 source "arch/arm/mach-mxs/Kconfig"
491 source "arch/arm/mach-nomadik/Kconfig"
493 source "arch/arm/mach-npcm/Kconfig"
495 source "arch/arm/mach-nspire/Kconfig"
497 source "arch/arm/mach-omap1/Kconfig"
499 source "arch/arm/mach-omap2/Kconfig"
501 source "arch/arm/mach-orion5x/Kconfig"
503 source "arch/arm/mach-pxa/Kconfig"
505 source "arch/arm/mach-qcom/Kconfig"
507 source "arch/arm/mach-rda/Kconfig"
509 source "arch/arm/mach-realtek/Kconfig"
511 source "arch/arm/mach-rpc/Kconfig"
513 source "arch/arm/mach-rockchip/Kconfig"
515 source "arch/arm/mach-s3c/Kconfig"
517 source "arch/arm/mach-s5pv210/Kconfig"
519 source "arch/arm/mach-sa1100/Kconfig"
521 source "arch/arm/mach-shmobile/Kconfig"
523 source "arch/arm/mach-socfpga/Kconfig"
525 source "arch/arm/mach-spear/Kconfig"
527 source "arch/arm/mach-sti/Kconfig"
529 source "arch/arm/mach-stm32/Kconfig"
531 source "arch/arm/mach-sunplus/Kconfig"
533 source "arch/arm/mach-sunxi/Kconfig"
535 source "arch/arm/mach-tegra/Kconfig"
537 source "arch/arm/mach-uniphier/Kconfig"
539 source "arch/arm/mach-ux500/Kconfig"
541 source "arch/arm/mach-versatile/Kconfig"
543 source "arch/arm/mach-vt8500/Kconfig"
545 source "arch/arm/mach-zynq/Kconfig"
547 # ARMv7-M architecture
556 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
565 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
566 with a range of available cores like Cortex-M3/M4/M7.
593 default y if PXA27x || PXA3xx || ARCH_MMP
599 source "arch/arm/Kconfig-nommu"
605 default y
617 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
620 Executing a SWP instruction to read-only memory does not set bit 11
638 This option enables the workaround for the 430973 Cortex-A8
641 same virtual address, whether due to self-modifying code or virtual
642 to physical address re-mapping, Cortex-A8 does not recover from the
643 stale interworking branch prediction. This results in Cortex-A8
648 available in non-secure mode.
655 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
662 register may not be available in non-secure mode and thus is not
671 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
675 workaround disables the write-allocate mode for the L2 cache via the
677 may not be available in non-secure mode and thus is not available on
686 This option enables the workaround for the 742230 Cortex-A9
690 the diagnostic register of the Cortex-A9 which causes the DMB
693 register may not be available in non-secure mode and thus is not
702 This option enables the workaround for the 742231 Cortex-A9
704 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
709 register of the Cortex-A9 which reduces the linefill issuing
711 diagnostics register may not be available in non-secure mode and thus
718 default y
720 This option enables the workaround for the 643719 Cortex-A9 (prior to
730 This option enables the workaround for the 720789 Cortex-A9 (prior to
743 This option enables the workaround for the 743622 Cortex-A9
745 optimisation in the Cortex-A9 Store Buffer may lead to data
747 register of the Cortex-A9 which disables the Store Buffer
751 may not be available in non-secure mode and thus is not available on a
759 This option enables the workaround for the 751472 Cortex-A9 (prior
765 not be available in non-secure mode and thus is not available on
773 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
776 can populate the micro-TLB with a stale entry which may be hit with
784 This option enables the workaround for the 754327 Cortex-A9 (prior to
792 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
797 hit-under-miss enabled). It sets the undocumented bit 31 in
799 register, thus disabling hit-under-miss without putting the
808 affecting Cortex-A9 MPCore with two or more processors (all
821 This option enables the workaround for the 764319 Cortex A-9 erratum.
832 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
839 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
842 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
852 This option enables the workaround for the 773022 Cortex-A15
862 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
864 - Cortex-A12 852422: Execution of a sequence of instructions might
866 any Cortex-A12 cores yet.
875 This option enables the workaround for the 821420 Cortex-A12
879 deadlock when the VMOV instructions are issued out-of-order.
885 This option enables the workaround for the 825619 Cortex-A12
888 and Device/Strongly-Ordered loads and stores might cause deadlock
894 This option enables the workaround for the 857271 Cortex-A12
902 This option enables the workaround for the 852421 Cortex-A17
912 - Cortex-A17 852423: Execution of a sequence of instructions might
914 any Cortex-A17 cores yet.
915 This is identical to Cortex-A12 erratum 852422. It is a separate
923 This option enables the workaround for the 857272 Cortex-A17 erratum.
925 This is identical to Cortex-A12 erratum 857271. It is a separate
957 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
967 This option should be selected by machines which have an SMP-
970 The only effect of this option is to make the SMP-related
974 bool "Symmetric Multi-Processing"
984 If you say N here, the kernel will run on uni- and multiprocessor
990 See also <file:Documentation/arch/x86/i386/IO-APIC.rst>,
991 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
992 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
999 default y
1001 SMP kernels contain instructions which fail on non-SMP processors.
1021 default y
1028 bool "Multi-core scheduler support"
1031 Multi-core scheduler support improves the CPU scheduler's decision
1032 making when dealing with multi-core CPU chips at a cost of slightly
1061 bool "Multi-Cluster Power Management"
1065 for (multi-)cluster based systems, such as big.LITTLE based
1073 to 2 clusters by default.
1105 default VMSPLIT_3G
1125 default PHYS_OFFSET if !MMU
1126 default 0x40000000 if VMSPLIT_1G
1127 default 0x80000000 if VMSPLIT_2G
1128 default 0xB0000000 if VMSPLIT_3G_OPT
1129 default 0xC0000000
1134 default 0x1f000000 if PAGE_OFFSET=0x40000000
1135 default 0x5f000000 if PAGE_OFFSET=0x80000000
1136 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1137 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1138 default 0xffffffff
1141 int "Maximum number of CPUs (2-32)"
1145 default "4"
1149 debugging is enabled, which uses half of the per-CPU fixmap
1153 bool "Support for hot-pluggable CPUs"
1166 implementing the PSCI specification for CPU-centric power
1173 default 128 if SOC_AT91RM9200
1174 default 0
1202 default HZ_FIXED if HZ_FIXED != 0
1203 default 100 if HZ_100
1204 default 200 if HZ_200
1205 default 250 if HZ_250
1206 default 300 if HZ_300
1207 default 500 if HZ_500
1208 default 1000
1214 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1216 default y if CPU_THUMBONLY
1220 Thumb-2 mode.
1227 default y
1245 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1267 (only for non "thumb" binaries). This option adds a tiny
1310 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1312 default y
1318 user-space 2nd level page tables to reside in high memory.
1321 bool "Enable use of CPU domains to implement privileged no-access"
1323 default y
1327 use-after-free bugs becoming an exploitable privilege escalation
1331 CPUs with low-vector mappings use a best-efforts implementation.
1343 default y
1354 Disabling this is usually safe for small single-platform
1359 default "11" if SOC_AM33XX
1360 default "8" if SA1111
1361 default "10"
1367 overriding the default setting when ability to allocate very
1378 address divisible by 4. On 32-bit ARM processors, these non-aligned
1381 correct operation of some network protocols. With an IP-only
1387 default y if CPU_FEROCEON
1390 cores where a 8-word STM instruction give significantly higher
1397 However, if the CPU data cache is using a write-allocate mode,
1437 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1444 default y
1471 default y
1489 default 0x0
1491 The physical address at which the ROM-able zImage is to be
1493 ROM-able zImage formats normally set this to a suitable
1500 default 0x0
1503 for the ROM-able zImage which must be available while the
1506 Platforms which normally make use of ROM-able zImage formats
1553 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1558 Uses the command-line options passed by the boot loader instead of
1565 The command-line arguments provided by the boot loader will be
1571 string "Default kernel command string"
1572 default ""
1576 architectures, you should supply some command-line options at build
1582 default CMDLINE_FROM_BOOTLOADER
1587 Uses the command-line options passed by the boot loader. If
1588 the boot loader doesn't provide any, the default kernel command
1594 The command-line arguments provided by the boot loader will be
1595 appended to the default kernel command string.
1598 bool "Always use the default kernel command string"
1600 Always use the default kernel command string, even if the boot
1603 command-line options your boot loader passes to the kernel.
1607 bool "Kernel Execute-In-Place from ROM"
1611 Execute-In-Place allows the kernel to run from non-volatile storage
1614 to RAM. Read-write sections, such as the data section and stack,
1631 default "0x00080000"
1654 default y
1664 default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
1668 will be determined at run-time, either by masking the current IP
1686 by UEFI firmware (such as non-volatile variables, realtime
1695 default y
1701 continue to boot on existing non-UEFI platforms.
1707 to be enabled much earlier than we do on ARM, which is non-trivial.
1730 your machine has an FPA or floating point co-processor podule.
1739 Say Y to include 80-bit support in the kernel floating-point
1740 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1741 Note that gcc does not generate 80-bit operations by default,
1754 It is very simple, and approximately 3-6 times faster than NWFPE.
1762 bool "VFP-format floating point maths"
1768 Please see <file:Documentation/arch/arm/vfp/release-notes.rst> for
1776 default y if CPU_V7
1809 default y if ARCH_SUSPEND_POSSIBLE