Lines Matching +full:sm8550 +full:- +full:lpass +full:- +full:lpi +full:- +full:pinctrl

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-lpass-lpi-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SM8550 SoC LPASS LPI TLMM
10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
11 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
15 (LPASS) Low Power Island (LPI) of Qualcomm SM8550 SoC.
19 const: qcom,sm8550-lpass-lpi-pinctrl
23 - description: LPASS LPI TLMM Control and Status registers
24 - description: LPASS LPI MCC registers
28 - description: LPASS Core voting clock
29 - description: LPASS Audio voting clock
31 clock-names:
33 - const: core
34 - const: audio
36 gpio-controller: true
38 "#gpio-cells":
40 include/dt-bindings/gpio/gpio.h
43 gpio-ranges:
47 "-state$":
49 - $ref: "#/$defs/qcom-sm8550-lpass-state"
50 - patternProperties:
51 "-pins$":
52 $ref: "#/$defs/qcom-sm8550-lpass-state"
56 qcom-sm8550-lpass-state:
59 Pinctrl node's client devices use subnodes for desired pin configuration.
61 $ref: /schemas/pinctrl/pincfg-node.yaml
69 pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
84 drive-strength:
90 slew-rate:
99 bias-bus-hold: true
100 bias-pull-down: true
101 bias-pull-up: true
102 bias-disable: true
103 input-enable: true
104 output-high: true
105 output-low: true
108 - pins
109 - function
114 - $ref: pinctrl.yaml#
117 - compatible
118 - reg
119 - clocks
120 - clock-names
121 - gpio-controller
122 - "#gpio-cells"
123 - gpio-ranges
128 - |
129 #include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
131 lpass_tlmm: pinctrl@6e80000 {
132 compatible = "qcom,sm8550-lpass-lpi-pinctrl";
138 clock-names = "core", "audio";
140 gpio-controller;
141 #gpio-cells = <2>;
142 gpio-ranges = <&lpass_tlmm 0 0 23>;
144 tx-swr-sleep-clk-state {
147 drive-strength = <2>;
148 bias-pull-down;