bindings/pinctrl/qcom%2Csdx65-tlmm.yaml

1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10   - Vamsi krishna Lanka <quic_vamslank@quicinc.com>
17     const: qcom,sdx65-tlmm
25   interrupt-controller: true
26   "#interrupt-cells": true
27   gpio-controller: true
28   "#gpio-cells": true
29   gpio-ranges: true
31   gpio-reserved-ranges:
35   "-state$":
37       - $ref: "#/$defs/qcom-sdx65-tlmm-state"
38       - patternProperties:
39           "-pins$":
40             $ref: "#/$defs/qcom-sdx65-tlmm-state"
44   qcom-sdx65-tlmm-state:
47       Pinctrl node's client devices use subnodes for desired pin configuration.
48       Client device subnodes use below standard properties.
49     $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
58             - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$"
59 …     - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, sdc1_rclk ]
116       - pins
119   - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
122   - compatible
123   - reg
128   - |
129     #include <dt-bindings/interrupt-controller/arm-gic.h>
131         compatible = "qcom,sdx65-tlmm";
133         gpio-controller;
134         #gpio-cells = <2>;
135         gpio-ranges = <&tlmm 0 0 109>;
136         interrupt-controller;
137         #interrupt-cells = <2>;
140         gpio-wo-subnode-state {
145         uart-w-subnodes-state {
146             rx-pins {
149                 bias-pull-up;
152             tx-pins {
155                 bias-disable;