Lines Matching +full:gcc +full:- +full:sm8150
1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
21 - qcom,sc8180x-qmp-pcie-phy
22 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
23 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
24 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
25 - qcom,sdm845-qhp-pcie-phy
26 - qcom,sdm845-qmp-pcie-phy
27 - qcom,sdx55-qmp-pcie-phy
28 - qcom,sdx65-qmp-gen4x2-pcie-phy
29 - qcom,sm8150-qmp-gen3x1-pcie-phy
30 - qcom,sm8150-qmp-gen3x2-pcie-phy
31 - qcom,sm8250-qmp-gen3x1-pcie-phy
32 - qcom,sm8250-qmp-gen3x2-pcie-phy
33 - qcom,sm8250-qmp-modem-pcie-phy
34 - qcom,sm8350-qmp-gen3x1-pcie-phy
35 - qcom,sm8450-qmp-gen3x1-pcie-phy
36 - qcom,sm8450-qmp-gen4x2-pcie-phy
37 - qcom,sm8550-qmp-gen3x2-pcie-phy
38 - qcom,sm8550-qmp-gen4x2-pcie-phy
48 clock-names:
51 - const: aux
52 - const: cfg_ahb
53 - const: ref
54 - enum: [rchng, refgen]
55 - const: pipe
56 - const: pipediv2
57 - const: phy_aux
59 power-domains:
66 reset-names:
69 - const: phy
70 - const: phy_nocsr
72 vdda-phy-supply: true
74 vdda-pll-supply: true
76 vdda-qref-supply: true
78 qcom,4ln-config-sel:
79 description: PCIe 4-lane configuration
80 $ref: /schemas/types.yaml#/definitions/phandle-array
82 - items:
83 - description: phandle of TCSR syscon
84 - description: offset of PCIe 4-lane configuration register
85 - description: offset of configuration bit for this PHY
87 "#clock-cells":
90 clock-output-names:
93 "#phy-cells":
97 - compatible
98 - reg
99 - clocks
100 - clock-names
101 - resets
102 - reset-names
103 - vdda-phy-supply
104 - vdda-pll-supply
105 - "#clock-cells"
106 - clock-output-names
107 - "#phy-cells"
112 - if:
117 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
122 - description: port a
123 - description: port b
125 - qcom,4ln-config-sel
131 - if:
136 - qcom,sc8180x-qmp-pcie-phy
137 - qcom,sdm845-qhp-pcie-phy
138 - qcom,sdm845-qmp-pcie-phy
139 - qcom,sdx55-qmp-pcie-phy
140 - qcom,sm8150-qmp-gen3x1-pcie-phy
141 - qcom,sm8150-qmp-gen3x2-pcie-phy
142 - qcom,sm8250-qmp-gen3x1-pcie-phy
143 - qcom,sm8250-qmp-gen3x2-pcie-phy
144 - qcom,sm8250-qmp-modem-pcie-phy
145 - qcom,sm8350-qmp-gen3x1-pcie-phy
146 - qcom,sm8450-qmp-gen3x1-pcie-phy
147 - qcom,sm8450-qmp-gen3x2-pcie-phy
148 - qcom,sm8550-qmp-gen3x2-pcie-phy
149 - qcom,sm8550-qmp-gen4x2-pcie-phy
154 clock-names:
157 - if:
162 - qcom,sc8280xp-qmp-gen3x1-pcie-phy
163 - qcom,sc8280xp-qmp-gen3x2-pcie-phy
164 - qcom,sc8280xp-qmp-gen3x4-pcie-phy
169 clock-names:
172 - if:
177 - qcom,sa8775p-qmp-gen4x2-pcie-phy
178 - qcom,sa8775p-qmp-gen4x4-pcie-phy
183 clock-names:
186 - if:
191 - qcom,sm8550-qmp-gen4x2-pcie-phy
196 reset-names:
202 reset-names:
206 - |
207 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
210 compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
213 clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
214 <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
215 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
216 <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
217 <&gcc GCC_PCIE_2B_PIPE_CLK>,
218 <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
219 clock-names = "aux", "cfg_ahb", "ref", "rchng",
222 power-domains = <&gcc PCIE_2B_GDSC>;
224 resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
225 reset-names = "phy";
227 vdda-phy-supply = <&vreg_l6d>;
228 vdda-pll-supply = <&vreg_l4d>;
230 #clock-cells = <0>;
231 clock-output-names = "pcie_2b_pipe_clk";
233 #phy-cells = <0>;
237 compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
240 clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
241 <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
242 <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
243 <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
244 <&gcc GCC_PCIE_2A_PIPE_CLK>,
245 <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
246 clock-names = "aux", "cfg_ahb", "ref", "rchng",
249 power-domains = <&gcc PCIE_2A_GDSC>;
251 resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
252 reset-names = "phy";
254 vdda-phy-supply = <&vreg_l6d>;
255 vdda-pll-supply = <&vreg_l4d>;
257 qcom,4ln-config-sel = <&tcsr 0xa044 0>;
259 #clock-cells = <0>;
260 clock-output-names = "pcie_2a_pipe_clk";
262 #phy-cells = <0>;