History log of /openbmc/u-boot/drivers/timer/Makefile (Results 1 – 25 of 34)
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Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04
# 328e3f8a 21-Dec-2018 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-riscv

- Add DM drivers to support RISC-V CPU and timer, plus some bug fixes.
- Support SiFive UART
- Rename ax25-ae350 defconfig


# 60262cd0 12-Dec-2018 Bin Meng <bmeng.cn@gmail.com>

timer: Add generic driver for RISC-V privileged architecture defined timer

RISC-V privileged architecture v1.10 defines a real-time counter,
exposed as a memory-mapped machine-mode register - mtime.

timer: Add generic driver for RISC-V privileged architecture defined timer

RISC-V privileged architecture v1.10 defines a real-time counter,
exposed as a memory-mapped machine-mode register - mtime. mtime must
run at constant frequency, and the platform must provide a mechanism
for determining the timebase of mtime. The mtime register has a
64-bit precision on all RV32, RV64, and RV128 systems.

Different platform may have different implementation of the mtime
block hence an API riscv_get_time() is required by this driver for
platform codes to hide such implementation details. For example,
on some platforms mtime is provided by the CLINT module, while on
some other platforms a simple 'rdtime' can be used to get the timer
counter.

With this timer driver the U-Boot timer functionalities like delay
works correctly now.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>

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# e16c888f 28-Nov-2018 Tom Rini <trini@konsulko.com>

Merge branch '2018-11-28-master-imports'

- Add MediaTek support


# d3c3606c 14-Nov-2018 Ryder Lee <ryder.lee@mediatek.com>

timer: MediaTek: add timer driver for MediaTek SoCs

This patch adds clock source and clock event for the timer found
on the Mediatek SoCs.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-b

timer: MediaTek: add timer driver for MediaTek SoCs

This patch adds clock source and clock event for the timer found
on the Mediatek SoCs.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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# 4e710ebb 18-Sep-2018 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-dm

- MPC83xx device tree additions (CPU and RAM)
- Fix sandbox build error
- Sync bitrev with Linux
- Various ofnode/DT improvements


# 2c21749d 06-Aug-2018 Mario Six <mario.six@gdsys.cc>

timer: Add MPC83xx timer driver

Add a timer driver for the MPC83xx architecture.

Signed-off-by: Mario Six <mario.six@gdsys.cc>


# d259f975 06-Aug-2018 Mario Six <mario.six@gdsys.cc>

timer: Sort Makefile entries

Makefile entries should be sorted.

Signed-off-by: Mario Six <mario.six@gdsys.cc>


# a376702f 24-Aug-2018 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-socfpga


# 66011a08 18-Aug-2018 Marek Vasut <marex@denx.de>

timer: dw-apb: Add Designware APB timer driver

Add timer driver for the Designware APB Timer IP. This is present
for example on the Altera SoCFPGA chips.

Signed-off-by: Marek Vasut <marex@denx.de>

timer: dw-apb: Add Designware APB timer driver

Add timer driver for the Designware APB Timer IP. This is present
for example on the Altera SoCFPGA chips.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Ley Foon Tan <ley.foon.tan@intel.com>

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Revision tags: v2018.07
# 3b52847a 11-May-2018 Tom Rini <trini@konsulko.com>

Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.07

microblaze:
- Align defconfig

zynq:
- Rework fpga initialization and cpuinfo handling

zynqmp

Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze

Xilinx changes for v2018.07

microblaze:
- Align defconfig

zynq:
- Rework fpga initialization and cpuinfo handling

zynqmp:
- Add ZynqMP R5 support
- Wire and enable watchdog on zcu100-revC
- Setup MMU map for DDR at run time
- Show board info based on DT and cleanup IDENT_STRING

zynqmp tools:
- Add read partition support
- Add initial support for Xilinx bif format for boot.bin generation

mmc:
- Fix get_timer usage on 64bit cpus
- Add support for SD3.0 UHS mode

nand-zynq:
- Add support for 16bit buswidth
- Use address cycles from onfi params

scsi:
- convert ceva sata to UCLASS_AHCI

timer:
- Add Cadence TTC for ZynqMP r5

watchdog:
- Minor cadence driver cleanup

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# 72c37d12 17-Apr-2018 Michal Simek <michal.simek@xilinx.com>

timer: Add Cadence TTC timer counter support

This driver was tested on Xilinx ZynqMP SoC.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>


# 83d290c5 06-May-2018 Tom Rini <trini@konsulko.com>

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>

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Revision tags: v2018.03
# 5120a083 07-Feb-2018 Patrice Chotard <patrice.chotard@st.com>

timer: stm32: Add timer support for STM32 SoCs family

This timer driver is using GPT Timer (General Purpose Timer)
available on all STM32 SOCs family.
This driver can be used on STM32F4/F7 and H7 So

timer: stm32: Add timer support for STM32 SoCs family

This timer driver is using GPT Timer (General Purpose Timer)
available on all STM32 SOCs family.
This driver can be used on STM32F4/F7 and H7 SoCs family

Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

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Revision tags: v2018.01
# d36a27ad 29-Nov-2017 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-nds32


# fa3e354b 27-Nov-2017 Rick Chen <rickchen36@gmail.com>

ae3xx: timer: Rename AE3XX to ATCPIT100

ATCPIT100 is Andestech timer IP which is embeded
in AE3XX and AE250 boards. So rename AE3XX to
ATCPIT100 will be more make sence.

Signed-off-by: rick <rick@a

ae3xx: timer: Rename AE3XX to ATCPIT100

ATCPIT100 is Andestech timer IP which is embeded
in AE3XX and AE250 boards. So rename AE3XX to
ATCPIT100 will be more make sence.

Signed-off-by: rick <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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Revision tags: v2017.11
# 47edaea4 15-Aug-2017 Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com>

driver: timer: Add the Atmel PIT timer driver

Add the new Atmel PIT timer driver, which supports the driver model
and device tree.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>


# c1b62ba9 14-Aug-2017 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-rockchip


# 1168d2dd 28-Jul-2017 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

rockchip: timer: add device-model timer driver for RK3368 (and similar)

This adds a device-model driver for the timer block in the RK3368 (and
similar devices that share the same timer block, such a

rockchip: timer: add device-model timer driver for RK3368 (and similar)

This adds a device-model driver for the timer block in the RK3368 (and
similar devices that share the same timer block, such as the RK3288) for
the down-counting (i.e. non-secure) timers.

This allows us to configure U-Boot for the RK3368 in such a way that
we can run with the secure timer inaccessible or uninitialised (note
that the ARMv8 generic timer does not count, if the secure timer is
not enabled).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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# e9e5d9d2 28-Jul-2017 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

dm: timer: normalise SPL and TPL support

To fully support DM timer in SPL and TPL, we need a few things cleaned
up and normalised:
- inclusion of the uclass and drivers should be an all-or-nothing

dm: timer: normalise SPL and TPL support

To fully support DM timer in SPL and TPL, we need a few things cleaned
up and normalised:
- inclusion of the uclass and drivers should be an all-or-nothing
decision for each stage and under control of $(SPL_TPL_)TIMER
instead of having the two-level configuration with TIMER and
$(SPL_TPL_)TIMER_SUPPORT
- when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can
not be compiled in

This normalises configuration to $(SPL_TPL_)TIMER and moves the config
options to drivers/timer/Kconfig (and cleans up the collateral damage
to some defconfigs that had SPL_TIMER_SUPPORT enabled).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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# c2774e61 22-May-2017 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-nds32


# b841b6e9 18-May-2017 rick <rick@andestech.com>

nds32: Support AE3XX platform.

Support Andestech AE3xx platform: serial, timer device tree flow.

Signed-off-by: rick <rick@andestech.com>


# f5076f86 16-May-2017 rick <rick@andestech.com>

nds32: Support AG101P timer DM.

Support AG101P timer device tree flow.

Signed-off-by: rick <rick@andestech.com>


# 20699e6b 21-Mar-2017 Vlad Zakharov <vzakhar@synopsys.com>

drivers: timer: Introduce ARC timer driver

This commit introduces timer driver for ARC.

ARC timers are configured via ARC AUX registers so we use special
functions to access timer control registers

drivers: timer: Introduce ARC timer driver

This commit introduces timer driver for ARC.

ARC timers are configured via ARC AUX registers so we use special
functions to access timer control registers.

This driver allows utilization of either timer0 or timer1
depending on which one is available in real hardware. Essentially
only existing timers should be mentioned in board's Device Tree
description.

Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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# 5cf618ee 24-Mar-2017 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-arc

This replaces legacy arch/arc/lib/timer.c implementation and allows us
to describe ARC Timers in Device Tree. Among other things that way we
may properly inherit T

Merge git://git.denx.de/u-boot-arc

This replaces legacy arch/arc/lib/timer.c implementation and allows us
to describe ARC Timers in Device Tree. Among other things that way we
may properly inherit Timer's clock from CPU's clock s they really run
synchronously.

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# ad9b5f77 21-Mar-2017 Vlad Zakharov <vzakhar@synopsys.com>

drivers: timer: Introduce ARC timer driver

This commit introduces timer driver for ARC.

ARC timers are configured via ARC AUX registers so we use special
functions to access timer control registers

drivers: timer: Introduce ARC timer driver

This commit introduces timer driver for ARC.

ARC timers are configured via ARC AUX registers so we use special
functions to access timer control registers.

This driver allows utilization of either timer0 or timer1
depending on which one is available in real hardware. Essentially
only existing timers should be mentioned in board's Device Tree
description.

Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

show more ...


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