| a27290a6 | 25-Sep-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: rk3188: ram: add support for 16bit row address
RK3188 using the same ddr_conf for both 15 bit and 16 bit row address.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Phili
rockchip: rk3188: ram: add support for 16bit row address
RK3188 using the same ddr_conf for both 15 bit and 16 bit row address.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
[Fixed compile-error by declaring 'row':]
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
show more ...
|
| f0768491 | 27-Sep-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: rk3328: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: P
rockchip: rk3328: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
show more ...
|
| c9eb7bca | 27-Sep-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: rk3288: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: P
rockchip: rk3288: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
show more ...
|
| 5b67d701 | 27-Sep-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: rk3188: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: P
rockchip: rk3188: move sdram driver to driver/ram
Since we have CONFIG_RAM framwork and its driver folder, move the driver
into it.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
show more ...
|
| 403e9cbc | 22-Jun-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: rk3368: add DRAM controller driver with DRAM initialisation
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM control
rockchip: rk3368: add DRAM controller driver with DRAM initialisation
This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).
At this stage, only the following feature-set is supported:
- DDR3
- 32-bit configuration (i.e. fully populated)
- dual-rank (i.e. no auto-detection of ranks)
- DDR3-1600K speed-bin
This driver expects to run from a TPL stage that will later return to
the RK3368 BROM. It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).
Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).
The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block. This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
|
| c336c3c3 | 28-Jun-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
spl: dm: Kconfig: introduce TPL_RAM (in analogy to SPL_RAM)
To allow finer grained selection of features for TPL, we introduce
TPL_RAM (in analogy to SPL_RAM).
Signed-off-by: Philipp Tomsich <phili
spl: dm: Kconfig: introduce TPL_RAM (in analogy to SPL_RAM)
To allow finer grained selection of features for TPL, we introduce
TPL_RAM (in analogy to SPL_RAM).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
show more ...
|
| f303aaf2 | 18-Jul-2017 |
Patrice Chotard <patrice.chotard@st.com> |
ram: stm32: add second SDRAM bank management
FMC is able to manage 2 SDRAM banks, but the current driver
implementation is only able to manage the first SDRAM bank.
Even if only bank2 is used, some
ram: stm32: add second SDRAM bank management
FMC is able to manage 2 SDRAM banks, but the current driver
implementation is only able to manage the first SDRAM bank.
Even if only bank2 is used, some bank1 registers must be
configured.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
|
| f39b90dc | 18-Jul-2017 |
Patrice Chotard <patrice.chotard@st.com> |
ram: stm32: replace fdtdec_get by ofnode calls
Replace all fdtdec_get..() calls by ofnode_read...() or dev_read..().
This will allow drivers to support a live device tree.
Signed-off-by: Patrice Ch
ram: stm32: replace fdtdec_get by ofnode calls
Replace all fdtdec_get..() calls by ofnode_read...() or dev_read..().
This will allow drivers to support a live device tree.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 1421e0a3 | 18-Jul-2017 |
Patrice Chotard <patrice.chotard@st.com> |
ram: stm32: get base address from DT
Retrieve RAM base address from DT instead of using STM32_SDRAM_FMC
For STM32F7, FMC block base address is 0xA0000000, but SDRAM
registers are located at offset
ram: stm32: get base address from DT
Retrieve RAM base address from DT instead of using STM32_SDRAM_FMC
For STM32F7, FMC block base address is 0xA0000000, but SDRAM
registers are located at offset 0x140 inside FMC block.
Update the stm32_fmc_regs fields with all FMC registers
to map SDRAM registers at the right address.
These additionals registers will be used later.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
show more ...
|