| #
e8f80a5a |
| 09-May-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-sunxi
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| #
83d290c5 |
| 06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borro
SPDX: Convert all of our single license tags to Linux Kernel style
When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.
In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.
This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.
Signed-off-by: Tom Rini <trini@konsulko.com>
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| #
161b1fe7 |
| 02-Feb-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-atmel
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| #
008e61f5 |
| 02-Feb-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
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| #
d2427caf |
| 01-Feb-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mips
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| #
9ffa7a35 |
| 28-Jan-2016 |
Purna Chandra Mandal <purna.mandal@microchip.com> |
drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.
This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rat
drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.
This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module.
DDR2 controller operates in half-rate mode (upto 533MHZ frequency).
Signed-off-by: Paul Thacker <paul.thacker@microchip.com>
Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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