247c80d6 | 28-Feb-2019 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
mv_ddr: ddr3: only use active chip-selects when tuning ODT
Inactive chip-selects will give invalid values for read_sample so don't consider them when trying to determine the overall min/max read sam
mv_ddr: ddr3: only use active chip-selects when tuning ODT
Inactive chip-selects will give invalid values for read_sample so don't consider them when trying to determine the overall min/max read sample.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
[https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/18] Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
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db363dbc | 09-May-2018 |
Chris Packham <chris.packham@alliedtelesis.co.nz> |
ARM: mvebu: a38x: use non-zero size for ddr scrubbing
Make ddr3_calc_mem_cs_size() global scope and use it in ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory.
Signed-off-by: Chris
ARM: mvebu: a38x: use non-zero size for ddr scrubbing
Make ddr3_calc_mem_cs_size() global scope and use it in ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
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00a77677 | 09-May-2018 |
Chris Packham <judge.packham@gmail.com> |
ARM: mvebu: a38x: remove some unused code
No in-tree code defines SUPPORT_STATIC_DUNIT_CONFIG or STATIC_ALGO_SUPPORT. Remove ddr3_a38x_mc_static.h and use unifdef to remove unused sections in the re
ARM: mvebu: a38x: remove some unused code
No in-tree code defines SUPPORT_STATIC_DUNIT_CONFIG or STATIC_ALGO_SUPPORT. Remove ddr3_a38x_mc_static.h and use unifdef to remove unused sections in the rest of the ddr/marvell/a38x code.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
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672e5598 | 17-Jan-2018 |
Chris Packham <judge.packham@gmail.com> |
ddr: marvell: update ddr controller init and freq
Update the calculation for tWR and tPD. This improves the DDR refresh interval and brings the initialization into line with the binary blobs current
ddr: marvell: update ddr controller init and freq
Update the calculation for tWR and tPD. This improves the DDR refresh interval and brings the initialization into line with the binary blobs currently being supplied by Marvell.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
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8bddf678 | 17-Jan-2018 |
Chris Packham <judge.packham@gmail.com> |
ddr: marvell: update additional ODT setting
The RD_SAMPLE_DELAY field is 5 bits so it needs to be masked with 0x1f instead of 0xf. Rather than checking the read sample delay for all DDR chip selects
ddr: marvell: update additional ODT setting
The RD_SAMPLE_DELAY field is 5 bits so it needs to be masked with 0x1f instead of 0xf. Rather than checking the read sample delay for all DDR chip selects use the values for the chip selects that are actually configured. Finally continue searching for the max_phase value even if the current read_sample is the same as the max_read_sample.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
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2efd27f7 | 17-Jan-2018 |
Chris Packham <judge.packham@gmail.com> |
ddr: marvell: use correct TREFI value
The ternary operation had the HIGH/LOW values the wrong way round. Update it to use the correct value.
Signed-off-by: Chris Packham <judge.packham@gmail.com> S
ddr: marvell: use correct TREFI value
The ternary operation had the HIGH/LOW values the wrong way round. Update it to use the correct value.
Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
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