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9a66328a |
| 11-May-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-tegra
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57a72d05 |
| 11-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Correct SPDX tags from recent xilinx merge Correct the SPDX tag format. Fixes: 3b52847a451a ("Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze")
SPDX: Correct SPDX tags from recent xilinx merge Correct the SPDX tag format. Fixes: 3b52847a451a ("Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze") Signed-off-by: Tom Rini <trini@konsulko.com>
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3b52847a |
| 11-May-2018 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze Xilinx changes for v2018.07 microblaze: - Align defconfig zynq: - Rework fpga initializat
Merge tag 'xilinx-for-v2018.07' of git://www.denx.de/git/u-boot-microblaze Xilinx changes for v2018.07 microblaze: - Align defconfig zynq: - Rework fpga initialization and cpuinfo handling zynqmp: - Add ZynqMP R5 support - Wire and enable watchdog on zcu100-revC - Setup MMU map for DDR at run time - Show board info based on DT and cleanup IDENT_STRING zynqmp tools: - Add read partition support - Add initial support for Xilinx bif format for boot.bin generation mmc: - Fix get_timer usage on 64bit cpus - Add support for SD3.0 UHS mode nand-zynq: - Add support for 16bit buswidth - Use address cycles from onfi params scsi: - convert ceva sata to UCLASS_AHCI timer: - Add Cadence TTC for ZynqMP r5 watchdog: - Minor cadence driver cleanup
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04ab29ab |
| 11-Apr-2018 |
Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
arm64: zynqmp: Add new defconfig for zc1275 revB This patch enables support zc1275 revB board. It has SD added compared to revA. The same configuration will work for RevC boards aswe
arm64: zynqmp: Add new defconfig for zc1275 revB This patch enables support zc1275 revB board. It has SD added compared to revA. The same configuration will work for RevC boards aswell. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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