History log of /openbmc/u-boot/board/phytec/pcl063/MAINTAINERS (Results 1 – 4 of 4)
Revision Date Author Comments
# db4a2999 31-Jan-2019 Tom Rini <trini@konsulko.com>

Merge tag 'video-updates-for-2019.04-rc1' of git://git.denx.de/u-boot-video

- ihs and imx driver fixes
- relax EDID validation checks for 0 hsync/vsync
pulse width (support some qu

Merge tag 'video-updates-for-2019.04-rc1' of git://git.denx.de/u-boot-video

- ihs and imx driver fixes
- relax EDID validation checks for 0 hsync/vsync
pulse width (support some quirky displays)

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# 552452f8 30-Jan-2019 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-sunxi

- Enable DM_MMC support


# 748ad078 30-Jan-2019 Tom Rini <trini@konsulko.com>

Merge tag 'u-boot-imx-20190129' of git://git.denx.de/u-boot-imx

For 2019.04


# 0963060c 11-Dec-2018 Martyn Welch <martyn@welchs.me.uk>

imx: Add PHYTEC phyBOARD-i.MX6UL-Segin

Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on
the PHYTEC phyCORE-i.MX6UL SOM (PCL063).

CPU: Freescale i.MX6

imx: Add PHYTEC phyBOARD-i.MX6UL-Segin

Port for the PHYTEC phyBOARD-i.MX6UL-Segin single board computer. Based on
the PHYTEC phyCORE-i.MX6UL SOM (PCL063).

CPU: Freescale i.MX6UL rev1.2 528 MHz (running at 396 MHz)
CPU: Industrial temperature grade (-40C to 105C) at 44C
Reset cause: POR
Board: PHYTEC phyCORE-i.MX6UL
I2C: ready
DRAM: 256 MiB
NAND: 512 MiB
MMC: FSL_SDHC: 0
In: serial
Out: serial
Err: serial
Net: FEC0

Working:
- Eth0
- i2C
- MMC/SD
- NAND
- UART (1 & 5)
- USB (host & otg)

Signed-off-by: Martyn Welch <martyn.welch@collabora.com>

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