Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04, v2018.07, v2018.03, v2018.01, v2017.11 |
|
#
07d77838 |
| 01-Aug-2017 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-x86
|
#
1df7f0b6 |
| 30-Jul-2017 |
Bin Meng <bmeng.cn@gmail.com> |
x86: kconfig: Let board select SPI flash
Only a specific type of SPI flash exists on a board, having board Kconfig to select the SPI flash seems to make more sense. Other flash types are not necessa
x86: kconfig: Let board select SPI flash
Only a specific type of SPI flash exists on a board, having board Kconfig to select the SPI flash seems to make more sense. Other flash types are not necessary except coreboot, which implies all available flash drivers there.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
|
Revision tags: v2016.07, openbmc-20160624-1 |
|
#
4edde961 |
| 14-Jan-2016 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-x86
|
#
fa331fad |
| 11-Dec-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: ivybridge: Do not require HAVE_INTEL_ME
Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot.
Signed-off-by: Bin Meng <b
x86: ivybridge: Do not require HAVE_INTEL_ME
Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
show more ...
|
#
789fa275 |
| 25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove HAVE_ACPI_RESUME
These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion.
Signed-off-by: Bin Meng <bmeng.cn@gmai
x86: Remove HAVE_ACPI_RESUME
These are currently dead codes. Until we have complete ACPI support, we don't know if it works or not. Remove to avoid confusion.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
show more ...
|
#
d475d590 |
| 25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove CPU_INTEL_SOCKET_RPGA989
This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRID
x86: Remove CPU_INTEL_SOCKET_RPGA989
This Kconfig option name indicates it has something to do with cpu socket, however it is actually not the case. Remove it and move options inside it to NORTHBRIDGE_INTEL_IVYBRIDGE.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
show more ...
|
#
efe2d80c |
| 25-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Clean up ivybridge/chrome Kconfig options
There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up.
S
x86: Clean up ivybridge/chrome Kconfig options
There are some options which are never used, and also some options which are selected by others but have never been a Kconfg option. Clean these up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
show more ...
|
Revision tags: v2016.01-rc1, v2015.10, v2015.10-rc5, v2015.10-rc4, v2015.10-rc3, v2015.10-rc2, v2015.10-rc1 |
|
#
f448c5d3 |
| 17-Jul-2015 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
|
#
605e15db |
| 15-Jul-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-x86
|
Revision tags: v2015.07 |
|
#
9e3a7c9b |
| 06-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove MARK_GRAPHICS_MEM_WRCOMB
MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code, hence remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromi
x86: Remove MARK_GRAPHICS_MEM_WRCOMB
MARK_GRAPHICS_MEM_WRCOMB is not referenced anywhere in the code, hence remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
Revision tags: v2015.07-rc3, v2015.07-rc2, v2015.07-rc1 |
|
#
b939689c |
| 05-May-2015 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
|
#
99556d7d |
| 27-Apr-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Kconfig: Remove deprecated CONFIG_SYS_EXTRA_OPTIONS
Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define the text base address. Since it is deprecated, just remove it and use C
x86: Kconfig: Remove deprecated CONFIG_SYS_EXTRA_OPTIONS
Currently all x86 boards still use CONFIG_SYS_EXTRA_OPTIONS to define the text base address. Since it is deprecated, just remove it and use CONFIG_SYS_TEXT_BASE directly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
Revision tags: v2015.04, v2015.04-rc5, v2015.04-rc4, v2015.04-rc3 |
|
#
51e9dad2 |
| 02-Mar-2015 |
Simon Glass <sjg@chromium.org> |
x86: Add support for panther (Asus Chromebox)
Support running U-Boot as a coreboot payload. Tested peripherals include:
- Video (HDMI and DisplayPort) - SATA disk - Gigabit Ethernet - SPI flash
US
x86: Add support for panther (Asus Chromebox)
Support running U-Boot as a coreboot payload. Tested peripherals include:
- Video (HDMI and DisplayPort) - SATA disk - Gigabit Ethernet - SPI flash
USB3 does not work. This may be a problem with the USB3 PCI driver or something in the USB3 stack and has not been investigated So far this is disabled. The SD card slot also does not work.
For video, coreboot will need to run the OPROM to set this up.
With this board, bare support (running without coreboot) is not available as yet.
Signed-off-by: Simon Glass <sjg@chromium.org>
show more ...
|