History log of /openbmc/u-boot/board/freescale/b4860qds/Makefile (Results 1 – 17 of 17)
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Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04, v2018.07
# 83d290c5 06-May-2018 Tom Rini <trini@konsulko.com>

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>

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Revision tags: v2018.03, v2018.01, v2017.11
# 6b29a395 29-Nov-2016 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-mpc85xx


# d46a4a13 18-Nov-2016 York Sun <york.sun@nxp.com>

powerpc: B4860QDS: Remove macro CONFIG_B4860QDS

Use CONFIG_TARGET_B4860QDS instead.

Signed-off-by: York Sun <york.sun@nxp.com>


Revision tags: v2016.07, openbmc-20160624-1
# dc557e9a 18-Jun-2016 Stefano Babic <sbabic@denx.de>

Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>


# cc749523 04-Jun-2016 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx


# 23d4e5ba 13-Apr-2016 Robert P. J. Day <rpjday@crashcourse.ca>

freescale: Tweak various Makefiles to remove redundancy, fix aesthetics

No intended functional change, just remove redundancies in some
Makefiles, and make whitespace aesthetics uniform.

Signed-off

freescale: Tweak various Makefiles to remove redundancy, fix aesthetics

No intended functional change, just remove redundancies in some
Makefiles, and make whitespace aesthetics uniform.

Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Reviewed-by: York Sun <york.sun@nxp.com>

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Revision tags: v2016.01-rc1, v2015.10, v2015.10-rc5, v2015.10-rc4, v2015.10-rc3, v2015.10-rc2, v2015.10-rc1, v2015.07, v2015.07-rc3, v2015.07-rc2, v2015.07-rc1, v2015.04, v2015.04-rc5, v2015.04-rc4, v2015.04-rc3, v2015.04-rc2, v2015.04-rc1, v2015.01, v2015.01-rc4, v2015.01-rc3, v2015.01-rc2, v2015.01-rc1, v2014.10, v2014.10-rc3, v2014.10-rc2, v2014.10-rc1, v2014.07, v2014.07-rc4, v2014.07-rc3, v2014.07-rc2
# e7f93505 15-May-2014 Stefano Babic <sbabic@denx.de>

Merge branch 'master' of git://git.denx.de/u-boot-arm


Revision tags: v2014.07-rc1
# d2a3e911 09-May-2014 Albert ARIBAUD <albert.u.boot@aribaud.net>

Merge branch 'u-boot/master'

Conflicts:
drivers/net/Makefile

(trivial merge)


# 080d8975 25-Apr-2014 Tom Rini <trini@ti.com>

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx


Revision tags: v2014.04
# c5dfe6ec 08-Apr-2014 Prabhakar Kushwaha <prabhakar@freescale.com>

board/b4qds:Add support of 2 stage NAND boot-loader

Add support of 2 stage NAND boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise D

board/b4qds:Add support of 2 stage NAND boot-loader

Add support of 2 stage NAND boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.

Initialise/create followings required for SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordingly

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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Revision tags: v2014.04-rc3, v2014.04-rc2, v2014.04-rc1, v2014.01, v2014.01-rc3, v2014.01-rc2, v2014.01-rc1
# 377e1048 20-Oct-2013 Masahiro Yamada <yamada.m@jp.panasonic.com>

board: powerpc: convert makefiles to Kbuild style

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: York Sun

board: powerpc: convert makefiles to Kbuild style

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: York Sun <yorksun@freescale.com>
Cc: Stefan Roese <sr@denx.de>

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Revision tags: v2013.10, v2013.10-rc4, v2013.10-rc3, v2013.10-rc2, v2013.10-rc1
# 326ea986 31-Jul-2013 Stefano Babic <sbabic@denx.de>

Merge git://git.denx.de/u-boot-arm

Conflicts:
board/freescale/mx6qsabrelite/Makefile
board/freescale/mx6qsabrelite/mx6qsabrelite.c
include/configs/mx6qsabrelite.h

Signed-off-by: Stefano Babic <s

Merge git://git.denx.de/u-boot-arm

Conflicts:
board/freescale/mx6qsabrelite/Makefile
board/freescale/mx6qsabrelite/mx6qsabrelite.c
include/configs/mx6qsabrelite.h

Signed-off-by: Stefano Babic <sbabic@denx.de>

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# 8b485ba1 25-Jul-2013 Albert ARIBAUD <albert.u.boot@aribaud.net>

Merge branch 'u-boot/master' into u-boot-arm/master


Revision tags: v2013.07, v2013.07-rc3
# 1a459660 08-Jul-2013 Wolfgang Denk <wd@denx.de>

Add GPL-2.0+ SPDX-License-Identifier to source files

Signed-off-by: Wolfgang Denk <wd@denx.de>
[trini: Fixup common/cmd_io.c]
Signed-off-by: Tom Rini <trini@ti.com>


Revision tags: v2013.07-rc2, v2013.07-rc1, v2013.04, v2013.04-rc3, v2013.04-rc2, v2013.04-rc1
# 9cd9b34d 23-Feb-2013 Stefano Babic <sbabic@denx.de>

Merge branch 'master' of git://git.denx.de/u-boot-arm


# 9a32084e 04-Feb-2013 Kim Phillips <kim.phillips@freescale.com>

Merge branch 'master' of git://git.denx.de/u-boot


Revision tags: v2013.01.01, v2013.01, v2013.01-rc3
# b5b06fb7 23-Dec-2012 York Sun <yorksun@freescale.com>

powerpc/b4860qds: Added Support for B4860QDS

B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor.

B4860QDS Ove

powerpc/b4860qds: Added Support for B4860QDS

B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architecture processor.

B4860QDS Overview
------------------
- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
ECC, 4 GB of memory in two ranks of 2 GB.
- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s, ECC, 2 GB of memory. Single rank.
- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
16x16 switch VSC3316
- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
8x8 switch VSC3308
- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
- B4860 UART port is available over USB-to-UART translator USB2SER or over
RS232 flat cable.
- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45 copper
connectors for Stand-alone mode and to the 1000Base-X over AMC MicroTCA
connector ports 0 and 2 for AMC mode.
- The B4860 configuration may be loaded from nine bits coded reset
configuration reset source. The RCW source is set by appropriate
DIP-switches:
- 16-bit NOR Flash / PROMJet
- QIXIS 8-bit NOR Flash Emulator
- 8-bit NAND Flash
- 24-bit SPI Flash
- Long address I2C EEPROM
- Available debug interfaces are:
- On-board eCWTAP controller with ETH and USB I/F
- JTAG/COP 16-pin header for any external TAP controller
- External JTAG source over AMC to support B2B configuration
- 70-pin Aurora debug connector
- QIXIS (FPGA) logic:
- 2 KB internal memory space including
- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
DDRCLK1, 2 and RTCCLK.
- Two 8T49N222A SerDes ref clock devices support two SerDes port clocks
- total four refclk, including CPRI clock scheme

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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