Revision tags: v00.04.15, v00.04.14, v00.04.13, v00.04.12, v00.04.11, v00.04.10, v00.04.09, v00.04.08, v00.04.07, v00.04.06, v00.04.05, v00.04.04, v00.04.03, v00.04.02, v00.04.01, v00.04.00, v2021.04, v00.03.03, v2021.01, v2020.10, v2020.07, v00.02.13, v2020.04, v2020.01, v2019.10, v00.02.05, v00.02.04, v00.02.03, v00.02.02, v00.02.01, v2019.07, v00.02.00, v2019.04 |
|
#
783e6681 |
| 27-Feb-2019 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-riscv
- SiFive FU540 Support
|
#
fdff1f96 |
| 25-Feb-2019 |
Anup Patel <Anup.Patel@wdc.com> |
riscv: Rename cpu/qemu to cpu/generic
The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for whi
riscv: Rename cpu/qemu to cpu/generic
The QEMU CPU support under arch/riscv is pretty much generic and works fine for SiFive Unleashed as well. In fact, there will be quite a few RISC-V SOCs for which QEMU CPU support will work fine.
This patch renames cpu/qemu to cpu/generic to indicate the above fact. If there are SOC specific errata workarounds required in cpu/generic then those can be done at runtime in cpu/generic based on CPU vendor specific DT compatible string.
Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
show more ...
|
#
328e3f8a |
| 21-Dec-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-riscv
- Add DM drivers to support RISC-V CPU and timer, plus some bug fixes. - Support SiFive UART - Rename ax25-ae350 defconfig
|
#
9acaf60b |
| 15-Dec-2018 |
Anup Patel <anup@brainfault.org> |
riscv: qemu: Imply SIFIVE_SERIAL for emulation
This patch enables SiFive UART driver for QEMU RISC-V emulation by implying SIFIVE_SERIAL on BOARD_SPECIFIC_OPTIONS.
Signed-off-by: Anup Patel <anup@b
riscv: qemu: Imply SIFIVE_SERIAL for emulation
This patch enables SiFive UART driver for QEMU RISC-V emulation by implying SIFIVE_SERIAL on BOARD_SPECIFIC_OPTIONS.
Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
show more ...
|
#
84304d48 |
| 12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: qemu: Add platform-specific Kconfig options
Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by:
riscv: qemu: Add platform-specific Kconfig options
Add the QEMU RISC-V platform-specific Kconfig options, to include CPU and timer drivers.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
show more ...
|
#
a77a8fde |
| 05-Dec-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-riscv
- Fix BBL may be corrupted problem. - Support U-Boot run in S-mode.
|
#
ef8c3d3f |
| 02-Dec-2018 |
Anup Patel <anup@brainfault.org> |
riscv: qemu: Use different SYS_TEXT_BASE for S-mode
When u-boot runs in S-mode, the M-mode runtime firmware (BBL or equivalent) uses memory range in 0x80000000 to 0x80200000. Due to this, we cannot
riscv: qemu: Use different SYS_TEXT_BASE for S-mode
When u-boot runs in S-mode, the M-mode runtime firmware (BBL or equivalent) uses memory range in 0x80000000 to 0x80200000. Due to this, we cannot use 0x80000000 as SYS_TEXT_BASE when running in S-mode. Instead for S-mode, we use 0x80200000 as SYS_TEXT_BASE.
Even Linux RISC-V kernel ignores/reserves memory range 0x80000000 to 0x80200000 because it runs in S-mode.
Signed-off-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
show more ...
|
#
ef0b75d3 |
| 26-Nov-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-riscv
|
#
897206c5 |
| 22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL
QEMU specifies the location of Linux (supplied with the -kernel argument) in the device tree using the riscv,kernel-start an
riscv: qemu: clear kernel-start/-end in device tree as workaround for BBL
QEMU specifies the location of Linux (supplied with the -kernel argument) in the device tree using the riscv,kernel-start and riscv,kernel-end properties. We currently rely on the SBI implementation of BBL to run Linux and therefore embed Linux as payload in BBL. This causes an issue, because BBL detects the kernel properties in the device tree and ignores the Linux payload as a result. Work around this issue by clearing the kernel properties in the device tree before booting Linux.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
show more ...
|
#
66ffe578 |
| 22-Nov-2018 |
Lukas Auer <lukas.auer@aisec.fraunhofer.de> |
riscv: qemu: detect and boot the kernel passed by QEMU
QEMU embeds the location of the kernel image in the device tree. Store this address in the environment as variable kernel_start. It is used in
riscv: qemu: detect and boot the kernel passed by QEMU
QEMU embeds the location of the kernel image in the device tree. Store this address in the environment as variable kernel_start. It is used in the board-local distro boot command QEMU to boot the kernel with the U-Boot device tree. The QEMU boot command is added as the first boot target device.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alexander Graf <agraf@suse.de>
show more ...
|
#
1d6edcbf |
| 16-Nov-2018 |
Tom Rini <trini@konsulko.com> |
Merge tag 'pull-14nov18' of git://git.denx.de/u-boot-dm
- virtio implementation and supporting patches - DM_FLAG_PRE_RELOC fixes - regmap improvements - minor buildman and sandbox things
|
#
440d9a47 |
| 15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: qemu: Include some useful commands
With the virtio net and blk drivers, we can do more stuff with some useful commands. Imply those in the board Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gm
riscv: qemu: Include some useful commands
With the virtio net and blk drivers, we can do more stuff with some useful commands. Imply those in the board Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
|
#
3c5196dc |
| 15-Oct-2018 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: qemu: Enumerate virtio bus during early boot
Currently devices on the virtio bus is not automatically enumerated, which means peripherals on the virtio bus are not discovered by their drivers
riscv: qemu: Enumerate virtio bus during early boot
Currently devices on the virtio bus is not automatically enumerated, which means peripherals on the virtio bus are not discovered by their drivers. This uses board_init() to do the virtio enumeration.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
|
#
94228a91 |
| 03-Oct-2018 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-riscv
- QEMU support
|
#
510e379c |
| 26-Sep-2018 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Add QEMU virt board support
This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V.
The QEMU virt machine models a generic RISC-V vir
riscv: Add QEMU virt board support
This adds QEMU RISC-V 'virt' board target support, with the hope of helping people easily test U-Boot on RISC-V.
The QEMU virt machine models a generic RISC-V virtual machine with support for the VirtIO standard networking and block storage devices. It has CLINT, PLIC, 16550A UART devices in addition to VirtIO and it also uses device-tree to pass configuration information to guest software. It implements RISC-V privileged architecture spec v1.10.
Both 32-bit and 64-bit builds are supported. Support is pretty much preliminary, only booting to U-Boot shell with the UART driver on a single core. Booting Linux is not supported yet.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
show more ...
|