History log of /openbmc/u-boot/arch/x86/cpu/braswell/Makefile (Results 1 – 12 of 12)
Revision Date Author Comments
# e8f80a5a 09-May-2018 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-sunxi


# 83d290c5 06-May-2018 Tom Rini <trini@konsulko.com>

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borro

SPDX: Convert all of our single license tags to Linux Kernel style

When U-Boot started using SPDX tags we were among the early adopters and
there weren't a lot of other examples to borrow from. So we picked the
area of the file that usually had a full license text and replaced it
with an appropriate SPDX-License-Identifier: entry. Since then, the
Linux Kernel has adopted SPDX tags and they place it as the very first
line in a file (except where shebangs are used, then it's second line)
and with slightly different comment styles than us.

In part due to community overlap, in part due to better tag visibility
and in part for other minor reasons, switch over to that style.

This commit changes all instances where we have a single declared
license in the tag as both the before and after are identical in tag
contents. There's also a few places where I found we did not have a tag
and have introduced one.

Signed-off-by: Tom Rini <trini@konsulko.com>

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# 2d5e6b4a 29-Oct-2017 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-video


# bb3d9ed3 27-Oct-2017 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-fsl-qoriq


# ae6ac0a0 27-Oct-2017 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-x86


# 4a5a7fca 18-Oct-2017 Bin Meng <bmeng.cn@gmail.com>

x86: braswell: Fix unexpected crash during Linux kernel boot

It was observed that when booting Linux kernel on Intel Cherry Hill
board, unexpected crash happens quite randomly. Sometimes

x86: braswell: Fix unexpected crash during Linux kernel boot

It was observed that when booting Linux kernel on Intel Cherry Hill
board, unexpected crash happens quite randomly. Sometimes kernel
just oops, while sometimes kernel throws MCE errors and hangs:

mce: [Hardware Error]: Machine check events logged
mce: [Hardware Error]: CPU 0: Machine Check: 0 Bank 4: c400000000010151
mce: [Hardware Error]: TSC 0 ADDR 130f3f2c0
mce: [Hardware Error]: PROCESSOR 0:406c3 TIME 1508160686 SOCKET 0 APIC 0 microcode 363

This looks like a hardware error per mcelog. After debugging, it
seems turning off turbo mode on the processor does not expose this
behavior, although U-Boot runs OK with turbo mode on. Suspect it is
related to an errata of Braswell processor.

To fix this, remove the Braswell cpu driver which does the turbo
mode configuration, and switch to use the generic cpu-x86 driver.
Also there is a configuration option in the FSP that turns on the
turbo mode and that has been turned off too.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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# 2dc5b553 21-Sep-2017 Tom Rini <trini@konsulko.com>

Merge branch 'next' of git://git.denx.de/u-boot-video


# e884656c 20-Sep-2017 Tom Rini <trini@konsulko.com>

Merge git://www.denx.de/git/u-boot-imx


# 45d19acb 18-Sep-2017 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-uniphier


# c07f3820 17-Sep-2017 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-x86


# fffad926 16-Aug-2017 Bin Meng <bmeng.cn@gmail.com>

x86: braswell: Add FSP configuration

Add FSP related configuration for Braswell.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>


# de9ac9a1 16-Aug-2017 Bin Meng <bmeng.cn@gmail.com>

x86: Add Intel Braswell SoC support

This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.

Similar to its predecessor BayTrail, there are som

x86: Add Intel Braswell SoC support

This adds initial Intel Braswell SoC support. It uses Intel FSP
to initialize the chipset.

Similar to its predecessor BayTrail, there are some work to do to
enable the legacy UART integrated in the Braswell SoC.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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