History log of /openbmc/u-boot/arch/riscv/cpu/Makefile (Results 1 – 5 of 5)
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# 328e3f8a 21-Dec-2018 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-riscv

- Add DM drivers to support RISC-V CPU and timer, plus some bug fixes.
- Support SiFive UART
- Rename ax25-ae350 defconfig


# 4b3f5ed5 12-Dec-2018 Bin Meng <bmeng.cn@gmail.com>

riscv: Move trap handler codes to mtrap.S

Currently the M-mode trap handler codes are in start.S. For future
extension, move them to a separate file mtrap.S.

Signed-off-by: Bin Meng <bmeng.cn@gmail

riscv: Move trap handler codes to mtrap.S

Currently the M-mode trap handler codes are in start.S. For future
extension, move them to a separate file mtrap.S.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Anup Patel <anup@brainfault.org>

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# 94228a91 03-Oct-2018 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-riscv

- QEMU support


# b5369c58 26-Sep-2018 Bin Meng <bmeng.cn@gmail.com>

riscv: Make start.S available for all targets

Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
common for all RISC-V targets.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by

riscv: Make start.S available for all targets

Currently start.S is inside arch/riscv/cpu/ax25/, but it can be
common for all RISC-V targets.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

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# 2fab2e9c 26-Sep-2018 Bin Meng <bmeng.cn@gmail.com>

riscv: Add a helper routine to print CPU information

This adds a helper routine to print CPU information. Currently
it prints all the instruction set extensions that the processor
core supports.

Si

riscv: Add a helper routine to print CPU information

This adds a helper routine to print CPU information. Currently
it prints all the instruction set extensions that the processor
core supports.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>

show more ...