History log of /openbmc/u-boot/arch/nios2/dts/include/dt-bindings/memory/rk3368-dmc.h (Results 1 – 6 of 6)
Revision Date Author Comments
# 56192959 18-Aug-2017 Tom Rini <trini@konsulko.com>

Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot

EFI Fixes for 2017.09:
- Fix GOP w/o display
- Fix LocateHandle
- Fix exit return value truncation
- Fix

Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot

EFI Fixes for 2017.09:
- Fix GOP w/o display
- Fix LocateHandle
- Fix exit return value truncation
- Fix missing EFIAPI in efi_locate_handle (for x86)

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# ceff355a 16-Aug-2017 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-sunxi

Update A20-OLinuXino-Lime2-eMMC_defconfig to include CONFIG_SCSI

Signed-off-by: Tom Rini <trini@konsulko.com>


# 470135be 16-Aug-2017 Tom Rini <trini@konsulko.com>

Merge git://www.denx.de/git/u-boot-imx

Update pfla02 for setenv changes and PHYLIB/etc migration to Kconfig.

Signed-off-by: Tom Rini <trini@konsulko.com>


# 390194d4 16-Aug-2017 Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-spi


# c1b62ba9 14-Aug-2017 Tom Rini <trini@konsulko.com>

Merge branch 'master' of git://git.denx.de/u-boot-rockchip


# 403e9cbc 22-Jun-2017 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

rockchip: rk3368: add DRAM controller driver with DRAM initialisation

This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled

rockchip: rk3368: add DRAM controller driver with DRAM initialisation

This adds a DRAM controller driver for the RK3368 and places it in
drivers/ram/rockchip (where the other DM-enabled DRAM controller
drivers for rockchip devices should also be moved eventually).

At this stage, only the following feature-set is supported:
- DDR3
- 32-bit configuration (i.e. fully populated)
- dual-rank (i.e. no auto-detection of ranks)
- DDR3-1600K speed-bin

This driver expects to run from a TPL stage that will later return to
the RK3368 BROM. It communicates with later stages through the
os_reg2 in the pmugrf (i.e. using the same mechanism as Rockchip's DDR
init code).

Unlike other DMC drivers for RK32xx and RK33xx parts, the required
timings are calculated within the driver based on a target frequency
and a DDR3 speed-bin (only the DDR3-1600K speed-bin is support at this
time).

The RK3368 also has the DDRC0_CON0 (DDR ch. 0, control-register 0)
register for controlling the operation of its (single-channel) DRAM
controller in the GRF block. This provides for selecting DDR3, mobile
DDR modes, and control low-power operation.
As part of this change, DDRC0_CON0 is also added to the GRF structure
definition (at offset 0x600).

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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