aa09a071 | 31-Oct-2018 |
Michael Trimarchi <michael@amarulasolutions.com> |
sunxi: Fix memory 2-rank initialization for a33 cpu
When we initialize the memory we need to autodetect rank and size but this can happen only if we send the proper reset to both memory module inclu
sunxi: Fix memory 2-rank initialization for a33 cpu
When we initialize the memory we need to autodetect rank and size but this can happen only if we send the proper reset to both memory module including cke signal. For this reason we need initialize the physical on both channel because we need to presume that both are connected. This way let the CLKE to be activated at the right time with the memory reset coming from the cpu
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
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0e21a2ff | 09-Nov-2018 |
Vasily Khoruzhick <anarsoul@gmail.com> |
sunxi-mmc: use new mode on both controllers on A64
Using new mode improves stability of eMMC and SD cards. Without it SPL fails to load u-boot from SD on Pinebook.
Signed-off-by: Vasily Khoruzhick
sunxi-mmc: use new mode on both controllers on A64
Using new mode improves stability of eMMC and SD cards. Without it SPL fails to load u-boot from SD on Pinebook.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Jagan Teki <jagan@amarulasolutions.com> # Amarula A64-Relic Reviewed-by: Jagan Teki <jagan@openedev.com>
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f8aa3f8d | 25-Oct-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sunxi: add Kconfig option for the maximum accessible DRAM
Allwinner 64-bit SoCs can use 4GiB DRAM chip, however their memory map has only allocated 3GiB for DRAM, so only 3GiB of the DRAM is accessi
sunxi: add Kconfig option for the maximum accessible DRAM
Allwinner 64-bit SoCs can use 4GiB DRAM chip, however their memory map has only allocated 3GiB for DRAM, so only 3GiB of the DRAM is accessible.
Add a Kconfig option for the maximum accessible DRAM.
For A80 it should be a much higher value (8GiB), but as I have no A80 device to test and originally U-Boot only supports 2GiB DRAM on A80, it currently still falls under the 2GiB situation.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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7009134c | 25-Oct-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sunxi: map DRAM part with 3G size
All Allwinner 64-bit SoCs now are known to be able to access 3GiB of external DRAM, however the size of DRAM part in the MMU translation table is still 2GiB.
Chang
sunxi: map DRAM part with 3G size
All Allwinner 64-bit SoCs now are known to be able to access 3GiB of external DRAM, however the size of DRAM part in the MMU translation table is still 2GiB.
Change the size of DRAM part in MMU table to 3GiB.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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c6c2c85e | 25-Oct-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sunxi: disable Pine A64 model detection code on other boards
The Pine A64 Plus/non-Plus model detection code is now built on all 64-bit ARM SoCs, even if the code cannot be triggered when H5/H6 is i
sunxi: disable Pine A64 model detection code on other boards
The Pine A64 Plus/non-Plus model detection code is now built on all 64-bit ARM SoCs, even if the code cannot be triggered when H5/H6 is in use.
Disable them when the board is Pine A64 by adding a Kconfig option that is only selected on Pine A64.
On GCC 7.3.1 this makes the size of the function reduces 184 bytes, and saves a 104 byte strstr() function, then makes SPL on H6 succeed to build.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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6f796a9b | 21-Jul-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sunxi: add support for Allwinner H6 SoC
Allwinner H6 is a new SoC from Allwinner features USB3 and PCIe interfaces.
This patch adds support for it.
The corresponding DTSI file, from Linux next-201
sunxi: add support for Allwinner H6 SoC
Allwinner H6 is a new SoC from Allwinner features USB3 and PCIe interfaces.
This patch adds support for it.
The corresponding DTSI file, from Linux next-20180720, is also introduced.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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da261654 | 22-Jul-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sunxi: add DRAM support to H6
The Allwinner H6 SoC comes with a set of new DRAM controller+PHY combo. Both the controller and the PHY seem to be originate from DesignWare, and are similar to the one
sunxi: add DRAM support to H6
The Allwinner H6 SoC comes with a set of new DRAM controller+PHY combo. Both the controller and the PHY seem to be originate from DesignWare, and are similar to the ones in ZynqMP SoCs.
This commit introduces an initial DRAM driver for H6, which contains only LPDDR3 support. The currently known SBCs with H6 all come with LPDDR3 memory, including Pine H64 and several Orange Pi's.
The BSP DRAM initialization code is closed source and violates GPL. Code in this commit is written by experimenting, referring the code/document of other users of the IPs (mainly the ZynqMP, as it's the only found PHY reference) and disassebling the BSP blob.
Thanks for Jernej Skrabec for review and fix some issues in this driver (including the most critical one which made it to work), and rewrite some code from register dump!
Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Acked-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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7f51a402 | 21-Jul-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sunxi: add UART0 setup for H6
The UART0 on H6 is available at PH bank (and PF bank, but the PF one is muxed with SD card).
Add pinmux configuration.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
sunxi: add UART0 setup for H6
The UART0 on H6 is available at PH bank (and PF bank, but the PF one is muxed with SD card).
Add pinmux configuration.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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10196c96 | 21-Jul-2018 |
Icenowy Zheng <icenowy@aosc.io> |
sunxi: use sun6i-style watchdog for H6
The H6 SoC has a sun6i-style watchdog in its timer part.
Enable the usage of it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxi
sunxi: use sun6i-style watchdog for H6
The H6 SoC has a sun6i-style watchdog in its timer part.
Enable the usage of it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
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f5871a66 | 25-May-2018 |
Jagan Teki <jagan@amarulasolutions.com> |
sunxi: Drop legacy usb_phy.c
Allwinner PHY USB code is now part of generic-phy framework, so drop existing legacy handling like arch/arm/mach-sunxi.c and related code areas.
Signed-off-by: Jagan Te
sunxi: Drop legacy usb_phy.c
Allwinner PHY USB code is now part of generic-phy framework, so drop existing legacy handling like arch/arm/mach-sunxi.c and related code areas.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Jun Nie <jun.nie@linaro.org>
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