History log of /openbmc/u-boot/arch/arm/mach-k3/Makefile (Results 1 – 7 of 7)
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# 5d5833af 26-Nov-2018 Tom Rini <trini@konsulko.com>

Merge branch '2018-11-26-master-imports'

- chiliboard updates
- misc TI platform updates


# ccdb7c22 14-Nov-2018 Lokesh Vutla <lokeshvutla@ti.com>

armv7r: K3: Allow SPL to run only on core 0

Based on the MCU R5 efuse settings, R5F cores in MCU domain
either work in split mode or in lock step mode.

If efuse settings are in lockstep mode: ROM r

armv7r: K3: Allow SPL to run only on core 0

Based on the MCU R5 efuse settings, R5F cores in MCU domain
either work in split mode or in lock step mode.

If efuse settings are in lockstep mode: ROM release R5 cores
and SPL continues to run on the R5 core is lockstep mode.

If efuse settings are in split mode: ROM releases both the R5
cores simultaneously and allow SPL to run on both the cores.
In this case it is bootloader's responsibility to detect core
1 and park it. Else both the core will be running bootloader
independently which might result in an unexpected behaviour.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

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# 0c4b382f 17-Nov-2018 Tom Rini <trini@konsulko.com>

Merge branch '2018-11-16-master-imports'

- Initial bcm968580xref, am65x_evm_r5 support
- lpc32xx, omap3_logic/am3517_evm updates
- pinctrl command
- fs_loader available for SPL


# a3501a4a 02-Nov-2018 Lokesh Vutla <lokeshvutla@ti.com>

armv7R: K3: am654: Add support to start ATF from R5 SPL

Considering the boot time requirements, Cortex-A core
should be able to start immediately after SPL on R5.
Add support for the same.

Reviewed

armv7R: K3: am654: Add support to start ATF from R5 SPL

Considering the boot time requirements, Cortex-A core
should be able to start immediately after SPL on R5.
Add support for the same.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

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# 23f7b1a7 02-Nov-2018 Lokesh Vutla <lokeshvutla@ti.com>

armv7R: K3: am654: Enable MPU regions

Enable MPU regions for AM654 evm:
- Region0: 0x00000000 - 0xFFFFFFFF: Device memory, not executable
- Region1: 0x41c00000 - 0x42400000: Normal, executable, WB,

armv7R: K3: am654: Enable MPU regions

Enable MPU regions for AM654 evm:
- Region0: 0x00000000 - 0xFFFFFFFF: Device memory, not executable
- Region1: 0x41c00000 - 0x42400000: Normal, executable, WB, Write alloc
- Region2: 0x80000000 - 0xFFFFFFFF: Normal, executable, WB, Write alloc
- region3-15: Disabled

With this dcache can be enabled either in SPL or U-Boot.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

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# e091832f 27-Aug-2018 Lokesh Vutla <lokeshvutla@ti.com>

armv8: K3: am654: Add custom MMU support

Add MMU mappings for AM654 SoC.

Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>


# ed0e6051 27-Aug-2018 Lokesh Vutla <lokeshvutla@ti.com>

arm: K3: Add support for AM654 SoC definition

The AM654 device is designed for industrial automation and PLC
controller class platforms among other applications. Introduce
base support for AM654 SoC

arm: K3: Add support for AM654 SoC definition

The AM654 device is designed for industrial automation and PLC
controller class platforms among other applications. Introduce
base support for AM654 SoC.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

show more ...