aspeed: Remove remaining "Aspeed secure boot" code

This was mostly removed from the SDK in b88f3710ee38 ("arm:
aspeed: ast2600: Remove ASPEED_LOADERS") when the
"AST2600 proprietary CoT" was abandon

aspeed: Remove remaining "Aspeed secure boot" code

This was mostly removed from the SDK in b88f3710ee38 ("arm:
aspeed: ast2600: Remove ASPEED_LOADERS") when the
"AST2600 proprietary CoT" was abandoned.

Signed-off-by: Joel Stanley <joel@jms.id.au>

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aspeed: Disable backdoor interfaces

On ast2400 and ast2500 we now disable the various hardware backdoor
interfaces as is done on ast2600. Two Kconfig options can selectively
re-enable some of these

aspeed: Disable backdoor interfaces

On ast2400 and ast2500 we now disable the various hardware backdoor
interfaces as is done on ast2600. Two Kconfig options can selectively
re-enable some of these interfaces: CONFIG_ASPEED_ENABLE_SUPERIO
leaves the ast2x00 built-in Super I/O device enabled, as it is
required for some systems, and CONFIG_ASPEED_ENABLE_DEBUG_UART leaves
the hardware debug UART enabled, since it provides a relatively high
ratio of utility to security risk during development.

This patch is based on a patch by Andrew Jeffery for an older u-boot
branch in the OpenBMC tree for the df-isolate-bmc distro feature flag.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Tested-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20220504004739.15829-1-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>

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ram: ast2600: align the RL and WL setting

Use macro to represent the RL and WL setting to ensure the PHY and
controller setting are aligned.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Ch

ram: ast2600: align the RL and WL setting

Use macro to represent the RL and WL setting to ensure the PHY and
controller setting are aligned.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I9151ef465ddb45b96bb0c5d61c01d516a92127c4

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aspeed: Fix typos in platform.h comments

"function" had been missing an "n" in a few places.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Link: https://lore.kernel.org/r/20220511025309.27224-1-

aspeed: Fix typos in platform.h comments

"function" had been missing an "n" in a few places.

Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Link: https://lore.kernel.org/r/20220511025309.27224-1-zev@bewilderbeest.net
Signed-off-by: Joel Stanley <joel@jms.id.au>

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remove h2x driver and add new pcie driver

Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Change-Id: I89ba3ac192641fecbf45c7d1eaf78f7dc9615c5a

clk: ast2600: Setup RGMII TX delay according to the DLY32 calculation

There is a duplicate DLY32 delay cell embedded in AST2600 SOC that is
the same with the one used for RGMII clock delay. The del

clk: ast2600: Setup RGMII TX delay according to the DLY32 calculation

There is a duplicate DLY32 delay cell embedded in AST2600 SOC that is
the same with the one used for RGMII clock delay. The delay time of
each tap delay can be measured by the embedded frequency counters
SCU320 and SCU330. So we can set up the TX delay according to the
runtime measured value to cover the chip-to-chip delay time variation.

v2: revise coding style

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I42c6cf09f36baf9ded22accf476cc93ae4991d86

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clk: ast2600: rework for the MAC interface delay

replace bitfield access by simple "FIELD_PREP" and bitshift operations
to meet kernel coding style.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech

clk: ast2600: rework for the MAC interface delay

replace bitfield access by simple "FIELD_PREP" and bitshift operations
to meet kernel coding style.

Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com>
Change-Id: I9956eafae0b88fd96143fa7ee61a88bd32579674

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ARM: aspeed: Update AST2600 SRAM size

AST2600 has additional 24KB SRAM size supported
since A1 revision.

ARM: Aspeed: Update SOC ID

ARM: aspeed: Update scu info for boot from eMMC

Add 2nd boot information for boot from eMMC feature.

ARM: Aspeed: update secure boot information

modify revision id base

update for send patch

add ast2400 clk

add ast2400

update ast2400 have 32kbyte

update hclk setting

fix fpga booting

boot0: aspeed: add image size header for boot form sram

secure: update bl2 verify

update bootflow

spl: ast2600: update secure boot flow

Copy all image to dram before verify, then boot from dram.

spl: ast2600: Add secure boot flow support

This patch refactors the AST2600 boot flow to support
both secure and normal boot in the consistent way.

aspeed: Fix compile warning

spi: cpuinfo: Add ABR, spi_aux_pin info

Add ABR, auxiliary pin and HW CRTM information log.