Merge git://www.denx.de/git/u-boot-imx

Signed-off-by: Tom Rini <trini@konsulko.com>

Merge git://git.denx.de/u-boot-arc

arc: cache: Add required NOPs after invalidation of instruction cache

As per ARC HS databook (see chapter 5.3.3.2) it is required to add
3 NOPs after each write to IC_IVIC which we do fr

arc: cache: Add required NOPs after invalidation of instruction cache

As per ARC HS databook (see chapter 5.3.3.2) it is required to add
3 NOPs after each write to IC_IVIC which we do from now on.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Eugeniy Paltsev <paltsev@synopsys.com>

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Merge git://git.denx.de/u-boot-arc

arcv2: Set IOC aperture so it covers available DDR

We used to use the same memory layout and size for a couple of
boards and thus we just hardcoding IOC aperture start and size.

arcv2: Set IOC aperture so it covers available DDR

We used to use the same memory layout and size for a couple of
boards and thus we just hardcoding IOC aperture start and size.

Now when we're getting more boards with more memory on board we
need to have an ability to set IOC so it matches real DDR layout
and size.

Even though it is not really a must but for simplicity we assume
IOC covers all the DDR we have, that gives us a chance to not
bother where DMA buffers are allocated - any part of DDR is OK.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

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Merge branch 'master' of git://www.denx.de/git/u-boot-imx

Drop CONFIG_STACKSIZE from include/configs/imx6_logic.h

Signed-off-by: Tom Rini <trini@konsulko.com>

ARCv2: SLC: Make sure busy bit is set properly on SLC flushing

As reported in STAR 9001165532, an SLC control reg read (for checking
busy state) right after SLC invalidate command may in

ARCv2: SLC: Make sure busy bit is set properly on SLC flushing

As reported in STAR 9001165532, an SLC control reg read (for checking
busy state) right after SLC invalidate command may incorrectly return
NOT busy causing software to NOT spin-wait while operation is underway.
(and for some reason this only happens if L1 cache is also disabled - as
required by IOC programming model)

Suggested workaround is to do an additional Control Reg read, which
ensures the 2nd read gets the right status.

Same fix made in Linux kernel:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c70c473396cbdec1168a6eff60e13029c0916854

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

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Merge git://git.denx.de/u-boot-nand-flash

Merge branch 'master' of git://git.denx.de/u-boot-socfpga

Merge branch 'master' of git://git.denx.de/u-boot-usb

Signed-off-by: Tom Rini <trini@konsulko.com>

Conflicts:
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h

Merge branch 'master' of git://www.denx.de/git/u-boot-imx

Merge branch 'master' of git://git.denx.de/u-boot-ubi

Merge branch 'master' of git://git.denx.de/u-boot-arc

arc/cache: Flush & invalidate all caches right before enabling IOC

According to ARC HS databook it is required to flush and disable
caches prior programming IOC registers. Otherwise ongo

arc/cache: Flush & invalidate all caches right before enabling IOC

According to ARC HS databook it is required to flush and disable
caches prior programming IOC registers. Otherwise ongoing coherent
memory operations may not observe the coherency protocols as
expected.

But since in ARC HS v2.1 there's no way to disable SLC (AKA L2 cache)
we're doing our best flushing and invalidating it.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

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arc/cache: really do invalidate_dcache_all() even if IOC exists

invalidate_dcache_all() could be used in different use-cases
and what is especially important most of those cases won't be

arc/cache: really do invalidate_dcache_all() even if IOC exists

invalidate_dcache_all() could be used in different use-cases
and what is especially important most of those cases won't be
related to DMAed data to or from peripherals, i.e. we'll be doing
invalidation of data used purely by CPU cores.

Given that IOC engine only snoops data that goes through DMA
we need to care ourselves about data used only by CPU cores
and so remove dependency on IOC from invalidate_dcache_all()
and always do real invalidation.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

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Merge branch 'master' of git://git.denx.de/u-boot-samsung

Merge branch 'master' of git://www.denx.de/git/u-boot-imx

Merge branch 'master' of git://git.denx.de/u-boot-ubi

Merge branch 'master' of git://git.denx.de/u-boot-x86

arc/cache: really do flush_dcache_all() even if IOC exists

flush_dcache_all() is used in the very end of U-Boot self relocation
to write back all copied and then patched code and data to

arc/cache: really do flush_dcache_all() even if IOC exists

flush_dcache_all() is used in the very end of U-Boot self relocation
to write back all copied and then patched code and data to their
new location in the very end of available memory space.

Since that has nothing to do with IO (i.e. no external DMA happens
here) IOC won't help here and we need to write back data cache contents
manually.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

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Merge branch 'master' of git://www.denx.de/git/u-boot-imx

Merge branch 'master' of git://git.denx.de/u-boot-atmel

arc: cache - utilize IO coherency (AKA IOC) engine

With release of ARC HS38 v2.1 new IO coherency engine could be built-in
ARC core. This hardware module ensures coherency between DMA-ed

arc: cache - utilize IO coherency (AKA IOC) engine

With release of ARC HS38 v2.1 new IO coherency engine could be built-in
ARC core. This hardware module ensures coherency between DMA-ed data
from peripherals and L2 cache.

With L2 and IOC enabled there's no overhead for L2 cache manual
maintenance which results in significantly improved IO bandwidth.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

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arc: cache - accommodate different L1 cache line lengths

ARC core could be configured with different L1 and L2 (AKA SLC) cache
line lengths. At least these values are possible and were r

arc: cache - accommodate different L1 cache line lengths

ARC core could be configured with different L1 and L2 (AKA SLC) cache
line lengths. At least these values are possible and were really used:
32, 64 or 128 bytes.

Current implementation requires cache line to be selected upon U-Boot
configuration and then it will only work on matching hardware. Indeed
this is quite efficient because cache line length gets hardcoded during
code compilation. But OTOH it makes binary less portable.

With this commit we allow U-Boot to determine real L1 cache line length
early in runtime and use this value later on. This extends portability
of U-Boot binary a lot.

Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>

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Merge branch 'master' of git://git.denx.de/u-boot