Fix spelling mistakes using codespell

This commit corrects various spelling mistakes throughout the
repository. The corrections were made automatically using `codespell`[1]
tool.

[1]: https://githu

Fix spelling mistakes using codespell

This commit corrects various spelling mistakes throughout the
repository. The corrections were made automatically using `codespell`[1]
tool.

[1]: https://github.com/codespell-project/codespell

Change-Id: Ifde736cdcf3ccca19b9e65afac69018628a19631
Signed-off-by: Manojkiran Eda <manojkiran.eda@gmail.com>

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sst: Don't always wake idle CPU

Some parts of SST are important (initial discovery, appliedConfig
change) and should use wake-on-PECI to ensure success even if the CPU is
in an idle PkgC state. Othe

sst: Don't always wake idle CPU

Some parts of SST are important (initial discovery, appliedConfig
change) and should use wake-on-PECI to ensure success even if the CPU is
in an idle PkgC state. Other parts are not important enough to justify
increasing the CPU power draw. Add a WakePolicy parameter to the
SSTInterface infrastructure to use a different policy in different
contexts.

Change-Id: I91435cc0357ab60ca4656e1bc51286e046ae3809
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

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Catch PECIErrors from supportsControl()

In future backend where supportsControl() requires a PECI call, make
sure any calls are inside a try/catch so potential errors are handled.

Change-Id: Ib3503

Catch PECIErrors from supportsControl()

In future backend where supportsControl() requires a PECI call, make
sure any calls are inside a try/catch so potential errors are handled.

Change-Id: Ib35030fa4df764a3cccd922099cd76c77823b7c4
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

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Update to the new sdbusplus namespace format

The sdbusplus namespace format was updated in [1]. This updates the
local namespaces to the new format.

[1]: https://github.com/openbmc/sdbusplus/commit

Update to the new sdbusplus namespace format

The sdbusplus namespace format was updated in [1]. This updates the
local namespaces to the new format.

[1]: https://github.com/openbmc/sdbusplus/commit/5011340e14da7fc04f8b20721c4631f778200edd

Change-Id: Ic6b874fb86d2ff2192d8067871bd2170696f2b8c
Signed-off-by: Jason M. Bills <jason.m.bills@intel.com>

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sst: Prefer cached values over default values

In anticipation of support for future CPUs, change some assumptions:
* When host is off, return cached property values instead of "default"
values. CP

sst: Prefer cached values over default values

In anticipation of support for future CPUs, change some assumptions:
* When host is off, return cached property values instead of "default"
values. CPUs may not guarantee support for level 0, so there is no
universal default.
* Must always check the backend interface is ready before using it.
* Rename numLevels() to maxLevel() since there may be discontinuities in
the supported levels.
* Also add some more debug prints.

Tested:
* On CPU that supports level 0 - verified that output of sst-info.sh
script was the same before and after these changes.
* On a CPU that only supports level 4 - verified that when host was
powered off, the AppliedConfig showed config4 (valid) instead of
config0 (invalid).

Change-Id: Idffcb9a6534ba32760f6d6b2ac244f47427995ea
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

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sdbusplus: use shorter type aliases

The sdbusplus headers provide shortened aliases for many types.
Switch to using them to provide better code clarity and shorter
lines. Possible replacements are

sdbusplus: use shorter type aliases

The sdbusplus headers provide shortened aliases for many types.
Switch to using them to provide better code clarity and shorter
lines. Possible replacements are for:
* bus_t
* exception_t
* manager_t
* match_t
* message_t
* object_t
* slot_t

Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Change-Id: Ibc88a5de1e7a11d332410985f29698b24aeae983

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cpuinfoapp: sst: Disallow BaseSpeedPriorityEnabled writes

The flow for dynamic OOB enabling of SST-BF is not working, so we need
to return errors if a user tries to modify BaseSpeedPriorityEnabled
i

cpuinfoapp: sst: Disallow BaseSpeedPriorityEnabled writes

The flow for dynamic OOB enabling of SST-BF is not working, so we need
to return errors if a user tries to modify BaseSpeedPriorityEnabled
instead of letting them get into an unsupported configuration.

Change-Id: I3a1d0162ce31db66a1a7d05e4a2a89827b5277f8
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

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sst: Rediscover profiles after host reboot

In some cases, host processor reboot may change the static SST-PP
profile information. This commit adds ability to register callbacks to
run upon hostState

sst: Rediscover profiles after host reboot

In some cases, host processor reboot may change the static SST-PP
profile information. This commit adds ability to register callbacks to
run upon hostState changes, and reruns SST discovery whenever the host
exits the power-off state.

Tested:
- Ran tools/sst-compare-redfish-os.py tool on platform with SPR host
CPU, and observed no mismatches before and after a host reboot.
- Confirmed Redfish OperatingConfig properties still populated when host
is off.

Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>
Change-Id: I9e7b0ebb8c5ec7a8464346f3476490b765579428

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Refactor SST host processor interface

In order to support future host processors that use a different
interface to SST, separate the SST logic into 1) high-level discovery
logic + D-Bus interfaces,

Refactor SST host processor interface

In order to support future host processors that use a different
interface to SST, separate the SST logic into 1) high-level discovery
logic + D-Bus interfaces, and 2) low-level backend processor interface.

This is a pure refactor with no functional change.

Tested:
Ran sst-compare-redfish-os.py tool on platform with SPR host CPU, and
verified no mismatches reported.
Used sst-info.sh to change configs and verify new config was reflected
in Redfish.

Change-Id: I6825eb7541cbe2214844e7b64d462f2688dedcec
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

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Defer PPIN read until BIOS enables it

On platforms with AST2600 BMC, we now boot fast enough to read the PPIN
over PECI before the BIOS has a chance to enable it (by default it is
not readable). Thi

Defer PPIN read until BIOS enables it

On platforms with AST2600 BMC, we now boot fast enough to read the PPIN
over PECI before the BIOS has a chance to enable it (by default it is
not readable). This commit delays the RdPkgConfig until BIOS is done
with POST.

Without this change, a value of 0 is read (and 0x90 CC - but that's
ignored), which causes us to drop it.

This also removes some unnecessary phosphor namespacing.

Tested:
- Booted from AC cycle, confirmed from journal logs that cpuinfoapp
delays an extra minute before running through getProcessorInfo. PPIN
is now set into SerialNumber D-Bus property and shown on Redfish.

Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>
Change-Id: Ie3e8c668c6b24b42ced22fd9e103d1518702d78a

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Add support for dynamic SST configuration change

- Implement the CurrentOperatingConfig getters to dynamically read
configuration via PECI. The approach is to read the value from
PECI for each D

Add support for dynamic SST configuration change

- Implement the CurrentOperatingConfig getters to dynamically read
configuration via PECI. The approach is to read the value from
PECI for each D-Bus read. When the host is off, return "default"
values, and when the host is on but the read fails, return the last
read (cached) values.
- Implement the CurrentOperatingConfig setters to modify configuration
via PECI.

Tested:
- Change SST-PP profile and SST-BF flag via D-Bus properties, and
confirmed that host-side Linux tool shows changes.
- Change while host off and confirm it's rejected.
- Change while host booting and confirm it's rejected.
- Read configuration while host off and confirm last known values are
returned.
- Read configuration while host booting and confirm actual values are
returned.
- Change on ICX after host booted and confirm it's rejected.

Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>
Change-Id: Ie6eed8ab23bff289e01d6d125402a5509d3a9110

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cpuinfoapp: Add SST discovery feature

Retrieve Intel Speed Select Technology (SST) configuration values for
all CPUs via PECI (OS-PCode mailbox). Each CPU may have up to three
Performance Profiles (

cpuinfoapp: Add SST discovery feature

Retrieve Intel Speed Select Technology (SST) configuration values for
all CPUs via PECI (OS-PCode mailbox). Each CPU may have up to three
Performance Profiles (PP), each with accompanying Base Frequency (BF)
information.

Discovery is started immediately, but if no CPUs are found or any
unexpected PECI error is encountered, discovery is aborted and scheduled
for periodic retries until complete.

The profile data is published on D-Bus using two predefined interfaces:
- xyz.openbmc_project.Control.Processor.CurrentOperationConfig, which
is implemented on each "cpu" object in the inventory, and contains
mutable properties for OOB configuration (modifiying properties not
supported yet).
- xyz.openbmc_project.Inventory.Item.Cpu.OperationConfig, which is
implemented on separate "config" objects and contains the readonly
properties for each performance profile.

Tested:
- Profiled performance of PECI operations via code instrumentation
(takes ~2 min per CPU on ast2500 during BMC boot, ~2 sec during BMC idle).
- Validated Redfish output against Linux driver using included python
tool.
- Injected PECI failures in code to test error handling, and tested
with Linux OS idling on host to make sure WOP is working.

Change-Id: I0d8ae79655dfd2880cf3bae6abe600597740df7c
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>

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