51139fb3 | 02-Oct-2021 |
Max Filippov <jcmvbkbc@gmail.com> |
tests/tcg/xtensa: allow testing big-endian cores
Don't disable all big-endian tests, instead check whether $(CORE) is supported by the configured $(QEMU) and enable tests if it is.
Signed-off-by: M
tests/tcg/xtensa: allow testing big-endian cores
Don't disable all big-endian tests, instead check whether $(CORE) is supported by the configured $(QEMU) and enable tests if it is.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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4be4c5b8 | 27-Apr-2022 |
Max Filippov <jcmvbkbc@gmail.com> |
tests/tcg/xtensa: fix vectors and checks in timer test
Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be a
tests/tcg/xtensa: fix vectors and checks in timer test
Timer test assumes that timer 0 IRQ has level 1 and other timers have higher level IRQs. This assumption is not correct and the levels may be arbitrary. Fix that assumption by providing TIMER*_VECTOR macro and using it for vector selection and by making the check for the timer exception cause conditional.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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da60ecd6 | 25-Apr-2022 |
Max Filippov <jcmvbkbc@gmail.com> |
tests/tcg/xtensa: enable mmu tests for MMUv3
MMU test suite is disabled for cores that have spanning TLB way, i.e. for all MMUv3 cores. Instead of disabling it make testing region virtual addresses
tests/tcg/xtensa: enable mmu tests for MMUv3
MMU test suite is disabled for cores that have spanning TLB way, i.e. for all MMUv3 cores. Instead of disabling it make testing region virtual addresses explicit and invalidate TLB mappings for entries that conflict with the test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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703cebcf | 25-Apr-2022 |
Max Filippov <jcmvbkbc@gmail.com> |
tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3
Autorefill tests in the phys_mem test suite are disabled for cores that have spanning TLB way, i.e. for all MMUv3 cores. Instead of disab
tests/tcg/xtensa: enable autorefill phys_mem tests for MMUv3
Autorefill tests in the phys_mem test suite are disabled for cores that have spanning TLB way, i.e. for all MMUv3 cores. Instead of disabling it invalidate TLB mappings for entries that conflict with the test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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e120c833 | 25-Apr-2022 |
Max Filippov <jcmvbkbc@gmail.com> |
tests/tcg/xtensa: remove dependency on the loop option
xtensa core may not have the loop option, but still have timers. Don't use loop opcode in the timer test.
Signed-off-by: Max Filippov <jcmvbkb
tests/tcg/xtensa: remove dependency on the loop option
xtensa core may not have the loop option, but still have timers. Don't use loop opcode in the timer test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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64407f6a | 25-Apr-2022 |
Max Filippov <jcmvbkbc@gmail.com> |
tests/tcg/xtensa: fix watchpoint test
xtensa core may have only one set of DBREAKA/DBREAKC registers. Don't hardcode register numbers in the test as 0 and 1, use macros that only index valid DBREAK*
tests/tcg/xtensa: fix watchpoint test
xtensa core may have only one set of DBREAKA/DBREAKC registers. Don't hardcode register numbers in the test as 0 and 1, use macros that only index valid DBREAK* registers.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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8164f14b | 24-Apr-2022 |
Max Filippov <jcmvbkbc@gmail.com> |
tests/tcg/xtensa: restore vecbase SR after test
Writing garbage into the vecbase SR results in hang in the subsequent tests that expect to raise an exception. Restore vecbase SR to its reset value a
tests/tcg/xtensa: restore vecbase SR after test
Writing garbage into the vecbase SR results in hang in the subsequent tests that expect to raise an exception. Restore vecbase SR to its reset value after the test.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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adbb3df0 | 04-Jul-2020 |
Max Filippov <jcmvbkbc@gmail.com> |
tests/tcg/xtensa: update test_lsc for DFPU
DFPU doesn't have pre-increment FP load/store opcodes, it has post-increment opcodes instead. Test increment opcodes present in the current config.
Signed
tests/tcg/xtensa: update test_lsc for DFPU
DFPU doesn't have pre-increment FP load/store opcodes, it has post-increment opcodes instead. Test increment opcodes present in the current config.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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7f4faa21 | 04-Jul-2020 |
Max Filippov <jcmvbkbc@gmail.com> |
tests/tcg/xtensa: update test_fp1 for DFPU
DFPU sets Invalid flag in FSR when at least one argument of FP comparison opcodes is NaN, SNaN for most opcodes, any NaN for olt/ole. Add checks for FSR an
tests/tcg/xtensa: update test_fp1 for DFPU
DFPU sets Invalid flag in FSR when at least one argument of FP comparison opcodes is NaN, SNaN for most opcodes, any NaN for olt/ole. Add checks for FSR and expected FSR values.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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5c10f488 | 30-Jun-2020 |
Max Filippov <jcmvbkbc@gmail.com> |
tests/tcg/xtensa: update test_fp0_conv for DFPU
DFPU conversion opcodes update FSR flags. Add FSR parameters and expected FSR register values for the conversion tests.
Signed-off-by: Max Filippov <
tests/tcg/xtensa: update test_fp0_conv for DFPU
DFPU conversion opcodes update FSR flags. Add FSR parameters and expected FSR register values for the conversion tests.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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ac81ff22 | 04-Jul-2020 |
Max Filippov <jcmvbkbc@gmail.com> |
tests/tcg/xtensa: expand madd tests
Test that madd doesn't do rounding after multiplication. Test NaN propagation rules for FPU2000 and DFPU madd opcode.
Signed-off-by: Max Filippov <jcmvbkbc@gmail
tests/tcg/xtensa: expand madd tests
Test that madd doesn't do rounding after multiplication. Test NaN propagation rules for FPU2000 and DFPU madd opcode.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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e95ef431 | 30-Jun-2020 |
Max Filippov <jcmvbkbc@gmail.com> |
tests/tcg/xtensa: update test_fp0_arith for DFPU
DFPU arithmetic opcodes update FSR flags. Add FSR parameters and expected FSR register values for the arithmetic tests.
Signed-off-by: Max Filippov
tests/tcg/xtensa: update test_fp0_arith for DFPU
DFPU arithmetic opcodes update FSR flags. Add FSR parameters and expected FSR register values for the arithmetic tests.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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2038f8c8 | 07-Aug-2019 |
Paolo Bonzini <pbonzini@redhat.com> |
tests/tcg: move configuration to a sub-shell script
Avoid the repeated inclusions of config-target.mak, which have risks of namespace pollution, and instead build minimal configuration files in a co
tests/tcg: move configuration to a sub-shell script
Avoid the repeated inclusions of config-target.mak, which have risks of namespace pollution, and instead build minimal configuration files in a configuration script. The same configuration files can also be included in Makefile and Makefile.qemu
[AJB 10/09/19] In the original PR this had inadvertently enabled tests for ppc64abi32. However as the rest of the multiarch tests work rather than disabling the otherwise correctly functioning build I've just skipped the failing linux-test test. For some reason I can't debug it with TCG so I'm leaving that to the PPC maintainers to look at.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20190807143523.15917-4-pbonzini@redhat.com> [AJB: s/docker/container/, rm last bits from configure, ppc6432abi hack] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Richard Henderson <rth@twiddle.net>
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