2f93ff31 | 05-Jul-2024 |
Richard Henderson <richard.henderson@linaro.org> |
tests/tcg/arm: Use vmrs/vmsr instead of mcr/mrc
Clang 14 generates
/home/rth/qemu/src/tests/tcg/arm/fcvt.c:431:9: error: invalid operand for instruction asm("mrc p10, 7, r1, cr1, cr0, 0\n\t"
tests/tcg/arm: Use vmrs/vmsr instead of mcr/mrc
Clang 14 generates
/home/rth/qemu/src/tests/tcg/arm/fcvt.c:431:9: error: invalid operand for instruction asm("mrc p10, 7, r1, cr1, cr0, 0\n\t" ^ <inline asm>:1:6: note: instantiated into assembly here mrc p10, 7, r1, cr1, cr0, 0 ^ /home/rth/qemu/src/tests/tcg/arm/fcvt.c:432:32: error: invalid operand for instruction "orr r1, r1, %[flags]\n\t" ^ <inline asm>:3:6: note: instantiated into assembly here mcr p10, 7, r1, cr1, cr0, 0 ^
This is perhaps a clang bug, but using the neon mnemonic is clearer.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20240630190050.160642-14-richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240705084047.857176-19-alex.bennee@linaro.org>
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e3693cd3 | 05-Jul-2024 |
Richard Henderson <richard.henderson@linaro.org> |
tests/tcg/arm: Use -march and -mfpu for fcvt
Clang requires the architecture to be set properly in order to assemble the half-precision instructions.
Signed-off-by: Richard Henderson <richard.hende
tests/tcg/arm: Use -march and -mfpu for fcvt
Clang requires the architecture to be set properly in order to assemble the half-precision instructions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20240630190050.160642-13-richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240705084047.857176-18-alex.bennee@linaro.org>
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1e7c9ba4 | 05-Jul-2024 |
Akihiko Odaki <akihiko.odaki@daynix.com> |
tests/tcg/arm: Manually register allocate half-precision numbers
Clang does not allow specifying an integer as the value of a single precision register. Explicitly move value from a general registe
tests/tcg/arm: Manually register allocate half-precision numbers
Clang does not allow specifying an integer as the value of a single precision register. Explicitly move value from a general register.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> [rth: Use one single inline asm block.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20240630190050.160642-12-richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240705084047.857176-17-alex.bennee@linaro.org>
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40126a16 | 05-Jul-2024 |
Richard Henderson <richard.henderson@linaro.org> |
tests/tcg/arm: Use -fno-integrated-as for test-arm-iwmmxt
Clang does not support IWMXT instructions. Fall back to the external assembler.
Signed-off-by: Richard Henderson <richard.henderson@linaro.
tests/tcg/arm: Use -fno-integrated-as for test-arm-iwmmxt
Clang does not support IWMXT instructions. Fall back to the external assembler.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20240630190050.160642-11-richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240705084047.857176-16-alex.bennee@linaro.org>
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8807477c | 05-Jul-2024 |
Richard Henderson <richard.henderson@linaro.org> |
tests/tcg/arm: Drop -N from LDFLAGS
This is redudant with a linker script, and is not supported by clang.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Akihiko Odaki
tests/tcg/arm: Drop -N from LDFLAGS
This is redudant with a linker script, and is not supported by clang.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20240630190050.160642-10-richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240705084047.857176-15-alex.bennee@linaro.org>
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3693408c | 05-Jul-2024 |
Akihiko Odaki <akihiko.odaki@daynix.com> |
tests/tcg/arm: Fix fcvt result messages
The test cases for "converting double-precision to single-precision" emits float but the result variable was typed as uint32_t and corrupted the printed value
tests/tcg/arm: Fix fcvt result messages
The test cases for "converting double-precision to single-precision" emits float but the result variable was typed as uint32_t and corrupted the printed values. Propertly type it as float.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Fixes: 8ec8a55e3fc9 ("tests/tcg/arm: add fcvt test cases for AArch32/64") Message-Id: <20240627-tcg-v2-1-1690a813348e@daynix.com> [rth: Update arm ref file as well] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20240630190050.160642-9-richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240705084047.857176-14-alex.bennee@linaro.org>
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8848c529 | 20-Nov-2023 |
Alex Bennée <alex.bennee@linaro.org> |
tests/tcg: enable semiconsole test for Arm
This still remains a MANUAL test due to blocking issues.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231120150833.2552739-13-alex.b
tests/tcg: enable semiconsole test for Arm
This still remains a MANUAL test due to blocking issues.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231120150833.2552739-13-alex.bennee@linaro.org>
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56611e17 | 20-Nov-2023 |
Alex Bennée <alex.bennee@linaro.org> |
tests/tcg: enable arm softmmu tests
To make it easier to test 32 bit Arm softmmu issues implement a basic boot.S so we can build the multiarch tests. Currently CHECK_UNALIGNED is disabled as I haven
tests/tcg: enable arm softmmu tests
To make it easier to test 32 bit Arm softmmu issues implement a basic boot.S so we can build the multiarch tests. Currently CHECK_UNALIGNED is disabled as I haven't got the right magic set for it to work.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20231120150833.2552739-12-alex.bennee@linaro.org>
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