06dd94e8 | 10-Sep-2024 |
Gustavo Romero <gustavo.romero@linaro.org> |
tests/tcg/aarch64: Extend MTE gdbstub tests to system mode
Extend MTE gdbstub tests to also run in system mode (share tests between user mode and system mode). The tests will only run if a version o
tests/tcg/aarch64: Extend MTE gdbstub tests to system mode
Extend MTE gdbstub tests to also run in system mode (share tests between user mode and system mode). The tests will only run if a version of GDB that supports MTE on baremetal is available in the test environment and if available compiler supports the 'memtag' flag (-march=armv8.5-a+memtag).
For the tests running in system mode, a page that supports MTE ops. is necessary. Therefore, an MTE-enabled page is made available (mapped) in the third 2 MB chunk of the second 1 GB space in the flat mapping set in boot.S. A new binary, mte.S, is also introduced for the tests. It links against boot.S and is executed by QEMU in system mode.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org> Message-Id: <20240906143316.657436-6-gustavo.romero@linaro.org> [AJB: fix stray _] Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240910173900.4154726-11-alex.bennee@linaro.org>
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3693408c | 05-Jul-2024 |
Akihiko Odaki <akihiko.odaki@daynix.com> |
tests/tcg/arm: Fix fcvt result messages
The test cases for "converting double-precision to single-precision" emits float but the result variable was typed as uint32_t and corrupted the printed value
tests/tcg/arm: Fix fcvt result messages
The test cases for "converting double-precision to single-precision" emits float but the result variable was typed as uint32_t and corrupted the printed values. Propertly type it as float.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Fixes: 8ec8a55e3fc9 ("tests/tcg/arm: add fcvt test cases for AArch32/64") Message-Id: <20240627-tcg-v2-1-1690a813348e@daynix.com> [rth: Update arm ref file as well] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20240630190050.160642-9-richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240705084047.857176-14-alex.bennee@linaro.org>
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b04bed52 | 05-Jul-2024 |
Richard Henderson <richard.henderson@linaro.org> |
tests/tcg/aarch64: Add -fno-integrated-as for sme
The only use of SME is inline assembly. Both gcc and clang only support SME with very recent releases; by deferring detection to the assembler we g
tests/tcg/aarch64: Add -fno-integrated-as for sme
The only use of SME is inline assembly. Both gcc and clang only support SME with very recent releases; by deferring detection to the assembler we get better test coverage.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20240630190050.160642-8-richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240705084047.857176-13-alex.bennee@linaro.org>
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69375de1 | 05-Jul-2024 |
Akihiko Odaki <akihiko.odaki@daynix.com> |
tests/tcg/aarch64: Fix irg operand type
irg expects 64-bit integers. Passing a 32-bit integer results in compilation failure with clang version 18.1.6.
Signed-off-by: Akihiko Odaki <akihiko.odaki@d
tests/tcg/aarch64: Fix irg operand type
irg expects 64-bit integers. Passing a 32-bit integer results in compilation failure with clang version 18.1.6.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20240627-tcg-v2-4-1690a813348e@daynix.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20240630190050.160642-6-richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240705084047.857176-11-alex.bennee@linaro.org>
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79e73b5d | 05-Jul-2024 |
Akihiko Odaki <akihiko.odaki@daynix.com> |
tests/tcg/aarch64: Explicitly specify register width
clang version 18.1.6 assumes a register is 64-bit by default and complains if a 32-bit value is given. Explicitly specify register width when pas
tests/tcg/aarch64: Explicitly specify register width
clang version 18.1.6 assumes a register is 64-bit by default and complains if a 32-bit value is given. Explicitly specify register width when passing a 32-bit value.
Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20240627-tcg-v2-3-1690a813348e@daynix.com> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20240630190050.160642-5-richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240705084047.857176-10-alex.bennee@linaro.org>
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e35562b3 | 05-Jul-2024 |
Richard Henderson <richard.henderson@linaro.org> |
tests/tcg/aarch64: Drop -fno-tree-loop-distribute-patterns
This option is not supported by clang, and is not required in order to get sve code generation with gcc 12.
Signed-off-by: Richard Henders
tests/tcg/aarch64: Drop -fno-tree-loop-distribute-patterns
This option is not supported by clang, and is not required in order to get sve code generation with gcc 12.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Akihiko Odaki <akihiko.odaki@daynix.com> Message-Id: <20240630190050.160642-4-richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20240705084047.857176-9-alex.bennee@linaro.org>
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8d37a142 | 20-Nov-2023 |
Peter Maydell <peter.maydell@linaro.org> |
target/arm: Handle overflow in calculation of next timer tick
In commit edac4d8a168 back in 2015 when we added support for the virtual timer offset CNTVOFF_EL2, we didn't correctly update the timer-
target/arm: Handle overflow in calculation of next timer tick
In commit edac4d8a168 back in 2015 when we added support for the virtual timer offset CNTVOFF_EL2, we didn't correctly update the timer-recalculation code that figures out when the timer interrupt is next going to change state. We got it wrong in two ways: * for the 0->1 transition, we didn't notice that gt->cval + offset can overflow a uint64_t * for the 1->0 transition, we didn't notice that the transition might now happen before the count rolls over, if offset > count
In the former case, we end up trying to set the next interrupt for a time in the past, which results in QEMU hanging as the timer fires continuously.
In the latter case, we would fail to update the interrupt status when we are supposed to.
Fix the calculations in both cases.
The test case is Alex Bennée's from the bug report, and tests the 0->1 transition overflow case.
Fixes: edac4d8a168 ("target-arm: Add CNTVOFF_EL2") Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/60 Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20231120173506.3729884-1-peter.maydell@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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