| #
a876b05d
|
| 04-Jul-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
Merge tag 'pull-aspeed-20250704' of https://github.com/legoater/qemu into staging
aspeed queue:
* Improved AST2700 SoC modeling (SDMC, SCU)
* Fixed hardware strapping of 'bletchley-bmc' machine
* A
Merge tag 'pull-aspeed-20250704' of https://github.com/legoater/qemu into staging
aspeed queue:
* Improved AST2700 SoC modeling (SDMC, SCU)
* Fixed hardware strapping of 'bletchley-bmc' machine
* Added new Meta 'catalina-bmc' machine and functional test using OpenBMC
* Improved AST2600 SCU protection key modeling
* Introduced AST2600 SCU unit tests
* Deprecated 'ast2700a0-evb' machine
* Added new NVIDIA 'gb200-bmc' machine and functional test using OpenBMC
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# gpg: Signature made Fri 04 Jul 2025 04:36:05 EDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full]
# gpg: aka "Cédric Le Goater <clg@kaod.org>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20250704' of https://github.com/legoater/qemu:
tests/functional: Add gb200 tests
hw/arm/aspeed: Add GB200 BMC target
docs: add support for gb200-bmc
hw/arm/aspeed: Add second SPI chip to Aspeed model
aspeed: Deprecate the ast2700a0-evb machine
tests/qtest: Add test for ASPEED SCU
hw/misc/aspeed_scu: Handle AST2600 protection key registers correctly
hw/arm/aspeed: add Catalina machine type
hw/arm/aspeed: bletchley: update hw strap values
hw/misc/aspeed_scu: Support the Frequency Counter Control register for AST2700
hw/misc/aspeed_sdmc: Skipping dram_init in u-boot for AST2700
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
show more ...
|
| #
8e076a3f
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| 19-Jun-2025 |
Patrick Williams <patrick@stwcx.xyz> |
hw/arm/aspeed: add Catalina machine type
Add the 'catalina-bmc' machine type based on the kernel DTS[1] as of
6.16-rc2. The i2c model is as complete as the current QEMU models
support, but in some
hw/arm/aspeed: add Catalina machine type
Add the 'catalina-bmc' machine type based on the kernel DTS[1] as of
6.16-rc2. The i2c model is as complete as the current QEMU models
support, but in some cases I substituted devices that are close enough
for present functionality. Strap registers are were verified with
hardware.
This has been tested with an openbmc image built from [2].
Add a functional test in line with Bletchley, pointing at an image
obtained from the OpenBMC Jenkins server.
[1]: https://github.com/torvalds/linux/blob/v6.16-rc2/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-catalina.dts
[2]: https://github.com/openbmc/openbmc/commit/5bc73ec261f981d5e586bda5ac78eb0cbd5f92b0
Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
Reviewed-by: Cédric Le Goater <clg@redhat.com>
Link: https://lore.kernel.org/qemu-devel/20250619151458.2831859-1-patrick@stwcx.xyz
Signed-off-by: Cédric Le Goater <clg@redhat.com>
show more ...
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