5d525294 | 07-Nov-2024 |
Jonathan Cameron <Jonathan.Cameron@huawei.com> |
bios-tables-test: Add data for complex numa test (GI, GP etc)
Given this is a new configuration, there are affects on APIC, CEDT and DSDT, but the key elements are in SRAT (plus related data in HMAT
bios-tables-test: Add data for complex numa test (GI, GP etc)
Given this is a new configuration, there are affects on APIC, CEDT and DSDT, but the key elements are in SRAT (plus related data in HMAT). The configuration has node to exercise many different combinations.
0) CPUs + Memory 1) GI only 2) GP only 3) CPUS only 4) Memory only 5) CPUs + HP memory
GI node, GP Node, Memory only node, hotplug memory only node, latency and bandwidth such that in Linux Access0 (any initiator) and Access1 (CPU initiators only) given different answers. Following cropped to remove details of each entry.
[000h 0000 004h] Signature : "SRAT" [System Resource Affinity Table] ... [030h 0048 001h] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] ... [032h 0050 001h] Proximity Domain Low(8) : 00 [033h 0051 001h] Apic ID : 00 ... [040h 0064 001h] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] ... [042h 0066 001h] Proximity Domain Low(8) : 03 [043h 0067 001h] Apic ID : 01 ... [050h 0080 001h] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] ... [052h 0082 001h] Proximity Domain Low(8) : 05 [053h 0083 001h] Apic ID : 02 ... [060h 0096 001h] Subtable Type : 01 [Memory Affinity] ... [062h 0098 004h] Proximity Domain : 00000000 ... [068h 0104 008h] Base Address : 0000000000000000 [070h 0112 008h] Address Length : 00000000000A0000 ... [088h 0136 001h] Subtable Type : 01 [Memory Affinity] ... [08Ah 0138 004h] Proximity Domain : 00000000 ... [090h 0144 008h] Base Address : 0000000000100000 [098h 0152 008h] Address Length : 0000000003F00000 ... [0B0h 0176 001h] Subtable Type : 01 [Memory Affinity] ... [0B2h 0178 004h] Proximity Domain : 00000004 ... [0B8h 0184 008h] Base Address : 0000000004000000 [0C0h 0192 008h] Address Length : 0000000004000000 ... some zero length entries follow...
[1A0h 0416 001h] Subtable Type : 05 [Generic Initiator Affinity] [1A1h 0417 001h] Length : 20
[1A2h 0418 001h] Reserved1 : 00 [1A3h 0419 001h] Device Handle Type : 01 [1A4h 0420 004h] Proximity Domain : 00000001 [1A8h 0424 010h] Device Handle : 00 00 01 02 00 00 00 00 00 00 00 00 00 00 00 00 [1B8h 0440 004h] Flags (decoded below) : 00000001 Enabled : 1 Architectural Transactions : 0 [1BCh 0444 004h] Reserved2 : 00000000
[1C0h 0448 001h] Subtable Type : 06 [Generic Port Affinity] [1C1h 0449 001h] Length : 20
[1C2h 0450 001h] Reserved1 : 00 [1C3h 0451 001h] Device Handle Type : 00 [1C4h 0452 004h] Proximity Domain : 00000002 [1C8h 0456 010h] Device Handle : 41 43 50 49 30 30 31 36 40 00 00 00 00 00 00 00 [1D8h 0472 004h] Flags (decoded below) : 00000001 Enabled : 1 Architectural Transactions : 0 [1DCh 0476 004h] Reserved2 : 00000000
[1E0h 0480 001h] Subtable Type : 01 [Memory Affinity] ... [1E2h 0482 004h] Proximity Domain : 00000005 ... [1E8h 0488 008h] Base Address : 0000000100000000 [1F0h 0496 008h] Address Length : 0000000090000000
Example block from HMAT: [0F0h 0240 002h] Structure Type : 0001 [System Locality Latency and Bandwidth Information] [0F2h 0242 002h] Reserved : 0000 [0F4h 0244 004h] Length : 00000078 [0F8h 0248 001h] Flags (decoded below) : 00 Memory Hierarchy : 0 Use Minimum Transfer Size : 0 Non-sequential Transfers : 0 [0F9h 0249 001h] Data Type : 03 [0FAh 0250 001h] Minimum Transfer Size : 00 [0FBh 0251 001h] Reserved1 : 00 [0FCh 0252 004h] Initiator Proximity Domains # : 00000004 [100h 0256 004h] Target Proximity Domains # : 00000006 [104h 0260 004h] Reserved2 : 00000000 [108h 0264 008h] Entry Base Unit : 0000000000000004 [110h 0272 004h] Initiator Proximity Domain List : 00000000 [114h 0276 004h] Initiator Proximity Domain List : 00000001 [118h 0280 004h] Initiator Proximity Domain List : 00000003 [11Ch 0284 004h] Initiator Proximity Domain List : 00000005 [120h 0288 004h] Target Proximity Domain List : 00000000 [124h 0292 004h] Target Proximity Domain List : 00000001 [128h 0296 004h] Target Proximity Domain List : 00000002 [12Ch 0300 004h] Target Proximity Domain List : 00000003 [130h 0304 004h] Target Proximity Domain List : 00000004 [134h 0308 004h] Target Proximity Domain List : 00000005 [138h 0312 002h] Entry : 00C8 [13Ah 0314 002h] Entry : 0000 [13Ch 0316 002h] Entry : 0032 [13Eh 0318 002h] Entry : 0000 [140h 0320 002h] Entry : 0032 [142h 0322 002h] Entry : 0064 [144h 0324 002h] Entry : 0019 [146h 0326 002h] Entry : 0000 [148h 0328 002h] Entry : 0064 [14Ah 0330 002h] Entry : 0000 [14Ch 0332 002h] Entry : 00C8 [14Eh 0334 002h] Entry : 0019 [150h 0336 002h] Entry : 0064 [152h 0338 002h] Entry : 0000 [154h 0340 002h] Entry : 0032 [156h 0342 002h] Entry : 0000 [158h 0344 002h] Entry : 0032 [15Ah 0346 002h] Entry : 0064 [15Ch 0348 002h] Entry : 0064 [15Eh 0350 002h] Entry : 0000 [160h 0352 002h] Entry : 0032 [162h 0354 002h] Entry : 0000 [164h 0356 002h] Entry : 0032 [166h 0358 002h] Entry : 00C8
Note the zeros represent entries where the target node has no memory. These could be surpressed but it isn't 'wrong' to provide them and it is (probably) permissible under ACPI to hotplug memory into these nodes later.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20241107123446.902801-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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4d62d15b | 04-Nov-2024 |
Salil Mehta <salil.mehta@huawei.com> |
tests/qtest/bios-tables-test: Update DSDT golden masters for x86/{pc,q35}
Update DSDT golden master files for x86/pc and x86/q35 platforms to accommodate changes made in the architecture-agnostic CP
tests/qtest/bios-tables-test: Update DSDT golden masters for x86/{pc,q35}
Update DSDT golden master files for x86/pc and x86/q35 platforms to accommodate changes made in the architecture-agnostic CPU AML. These updates notify the guest OS of vCPU hot-plug and hot-unplug status using the ACPI `_STA.Enabled` bit.
The following is a diff of the changes in the .dsl file generated with IASL:
@@ -1480,6 +1480,7 @@ CRMV, 1, CEJ0, 1, CEJF, 1, + CPRS, 1, Offset (0x05), CCMD, 8 } @@ -1514,9 +1515,16 @@ Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) \_SB.PCI0.PRES.CSEL = Arg0 Local0 = Zero - If ((\_SB.PCI0.PRES.CPEN == One)) - { - Local0 = 0x0F + If ((\_SB.PCI0.PRES.CPRS == One)) + { + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + Else + { + Local0 = 0x0D + } }
Release (\_SB.PCI0.PRES.CPLK)
Reported-by: Zhao Liu <zhao1.liu@intel.com> Signed-off-by: Salil Mehta <salil.mehta@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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9848a76c | 24-Sep-2024 |
Ricardo Ribalda <ribalda@chromium.org> |
tests/acpi: pc: update golden masters for DSDT
Note: since all we did is replace VarPackageOp with PackageOP, and both are represented by Package() in ASL, the AML is different but ASL is the same.
tests/acpi: pc: update golden masters for DSDT
Note: since all we did is replace VarPackageOp with PackageOP, and both are represented by Package() in ASL, the AML is different but ASL is the same.
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Message-Id: <20240924132417.739809-4-ribalda@chromium.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com>
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f91bb8ba | 08-Aug-2024 |
Haibo Xu <haibo1.xu@intel.com> |
tests/acpi: Add expected ACPI SRAT AML file for RISC-V
As per the step 5 in the process documented in bios-tables-test.c, generate the expected ACPI SRAT AML data file for RISC-V using the rebuild-e
tests/acpi: Add expected ACPI SRAT AML file for RISC-V
As per the step 5 in the process documented in bios-tables-test.c, generate the expected ACPI SRAT AML data file for RISC-V using the rebuild-expected-aml.sh script and update the bios-tables-test-allowed-diff.h.
This is a new file being added for the first time. Hence, iASL diff output is not added.
Signed-off-by: Haibo Xu <haibo1.xu@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <a667480203b35508038176c8ce4722370294cc57.1723172696.git.haibo1.xu@intel.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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e9c0d54f | 16-Jul-2024 |
Sunil V L <sunilvl@ventanamicro.com> |
tests/acpi: Add expected ACPI AML files for RISC-V
As per the step 5 in the process documented in bios-tables-test.c, generate the expected ACPI AML data files for RISC-V using the rebuild-expected-
tests/acpi: Add expected ACPI AML files for RISC-V
As per the step 5 in the process documented in bios-tables-test.c, generate the expected ACPI AML data files for RISC-V using the rebuild-expected-aml.sh script and update the bios-tables-test-allowed-diff.h.
These are all new files being added for the first time. Hence, iASL diff output is not added.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240716144306.2432257-10-sunilvl@ventanamicro.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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cc3ba242 | 16-Jul-2024 |
Sunil V L <sunilvl@ventanamicro.com> |
tests/acpi: Add empty ACPI data files for RISC-V
As per process documented (steps 1-3) in bios-tables-test.c, add empty AML data files for RISC-V ACPI tables and add the entries in bios-tables-test-
tests/acpi: Add empty ACPI data files for RISC-V
As per process documented (steps 1-3) in bios-tables-test.c, add empty AML data files for RISC-V ACPI tables and add the entries in bios-tables-test-allowed-diff.h.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20240716144306.2432257-8-sunilvl@ventanamicro.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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0af3dfa5 | 16-Jul-2024 |
Sunil V L <sunilvl@ventanamicro.com> |
tests/acpi: update expected DSDT blob for aarch64 and microvm
After PCI link devices are moved out of the scope of PCI root complex, the DSDT files of machines which use GPEX, will change. So, updat
tests/acpi: update expected DSDT blob for aarch64 and microvm
After PCI link devices are moved out of the scope of PCI root complex, the DSDT files of machines which use GPEX, will change. So, update the expected AML files with these changes for these machines.
Mainly, there are 2 changes.
1) Since the link devices are created now directly under _SB for all PCI root bridges in the system, they should have unique names. So, instead of GSIx, named those devices as LXXY where L means link, XX will have PCI bus number and Y will have the INTx number (ex: L000 or L001). The _PRT entries will also be updated to reflect this name change.
2) PCI link devices are moved from the scope of each PCI root bridge to directly under _SB.
Below is the sample iASL difference for one such link device.
Scope (\_SB) { Name (_HID, "LNRO0005") // _HID: Hardware ID Name (_UID, 0x1F) // _UID: Unique ID Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { Memory32Fixed (ReadWrite, 0x0A003E00, // Address Base 0x00000200, // Address Length ) Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { 0x0000004F, } })
+ Device (L000) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Name (_CRS, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + Device (PCI0) { Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID Name (_SEG, Zero) // _SEG: PCI Segment Name (_BBN, Zero) // _BBN: BIOS Bus Number Name (_UID, Zero) // _UID: Unique ID Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String Name (_CCA, One) // _CCA: Cache Coherency Attribute Name (_PRT, Package (0x80) // _PRT: PCI Routing Table {
Package (0x04) { 0xFFFF, Zero, - GSI0, + L000, Zero },
.....
})
Device (GSI0) { Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) Name (_UID, Zero) // _UID: Unique ID Name (_PRS, ResourceTemplate () { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { 0x00000023, } }) Name (_CRS, ResourceTemplate () { Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) { 0x00000023, } }) Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings { } } } }
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Message-Id: <20240716144306.2432257-6-sunilvl@ventanamicro.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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579094cb | 14-Mar-2024 |
Igor Mammedov <imammedo@redhat.com> |
tests: smbios: add test for legacy mode CLI options
Unfortunately having 2.0 machine type deprecated is not enough to get rid of legacy SMBIOS handling since 'isapc' also uses that and it's staying
tests: smbios: add test for legacy mode CLI options
Unfortunately having 2.0 machine type deprecated is not enough to get rid of legacy SMBIOS handling since 'isapc' also uses that and it's staying around.
Hence add test for CLI options handling to be sure that it ain't broken during SMBIOS code refactoring.
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Ani Sinha <anisinha@redhat.com> Tested-by: Fiona Ebner <f.ebner@proxmox.com> Message-Id: <20240314152302.2324164-4-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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ea2fde5b | 22-Jan-2024 |
Peter Maydell <peter.maydell@linaro.org> |
tests/qtest/bios-tables-tests: Update virt golden reference
Update the virt golden reference files to say that the FACP is ACPI v6.3, and the GTDT table is a revision 3 table with space for the virt
tests/qtest/bios-tables-tests: Update virt golden reference
Update the virt golden reference files to say that the FACP is ACPI v6.3, and the GTDT table is a revision 3 table with space for the virtual EL2 timer.
Diffs from iasl:
@@ -1,32 +1,32 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024 + * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024 * * ACPI Data Table [FACP] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */
[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 00000114 [008h 0008 1] Revision : 06 -[009h 0009 1] Checksum : 15 +[009h 0009 1] Checksum : 12 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 4] FACS Address : 00000000 [028h 0040 4] DSDT Address : 00000000 [02Ch 0044 1] Model : 00 [02Dh 0045 1] PM Profile : 00 [Unspecified] [02Eh 0046 2] SCI Interrupt : 0000 [030h 0048 4] SMI Command Port : 00000000 [034h 0052 1] ACPI Enable Value : 00 [035h 0053 1] ACPI Disable Value : 00 [036h 0054 1] S4BIOS Command : 00 [037h 0055 1] P-State Control : 00 @@ -86,33 +86,33 @@ Use APIC Physical Destination Mode (V4) : 0 Hardware Reduced (V5) : 1 Low Power S0 Idle (V5) : 0
[074h 0116 12] Reset Register : [Generic Address Structure] [074h 0116 1] Space ID : 00 [SystemMemory] [075h 0117 1] Bit Width : 00 [076h 0118 1] Bit Offset : 00 [077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] [078h 0120 8] Address : 0000000000000000
[080h 0128 1] Value to cause reset : 00 [081h 0129 2] ARM Flags (decoded below) : 0003 PSCI Compliant : 1 Must use HVC for PSCI : 1
-[083h 0131 1] FADT Minor Revision : 00 +[083h 0131 1] FADT Minor Revision : 03 [084h 0132 8] FACS Address : 0000000000000000 [08Ch 0140 8] DSDT Address : 0000000000000000 [094h 0148 12] PM1A Event Block : [Generic Address Structure] [094h 0148 1] Space ID : 00 [SystemMemory] [095h 0149 1] Bit Width : 00 [096h 0150 1] Bit Offset : 00 [097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] [098h 0152 8] Address : 0000000000000000
[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] [0A0h 0160 1] Space ID : 00 [SystemMemory] [0A1h 0161 1] Bit Width : 00 [0A2h 0162 1] Bit Offset : 00 [0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] [0A4h 0164 8] Address : 0000000000000000
@@ -164,34 +164,34 @@ [0F5h 0245 1] Bit Width : 00 [0F6h 0246 1] Bit Offset : 00 [0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] [0F8h 0248 8] Address : 0000000000000000
[100h 0256 12] Sleep Status Register : [Generic Address Structure] [100h 0256 1] Space ID : 00 [SystemMemory] [101h 0257 1] Bit Width : 00 [102h 0258 1] Bit Offset : 00 [103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] [104h 0260 8] Address : 0000000000000000
[10Ch 0268 8] Hypervisor ID : 00000000554D4551
Raw Table Data: Length 276 (0x114)
- 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BOCHS + 0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20 // FACP......BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ - 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............QEMU 0110: 00 00 00 00 // ....
@@ -1,32 +1,32 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20200925 (64-bit version) * Copyright (c) 2000 - 2020 Intel Corporation * - * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024 + * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024 * * ACPI Data Table [GTDT] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */
[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] -[004h 0004 4] Table Length : 00000060 -[008h 0008 1] Revision : 02 -[009h 0009 1] Checksum : 9C +[004h 0004 4] Table Length : 00000068 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 93 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001
[024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF [02Ch 0044 4] Reserved : 00000000
[030h 0048 4] Secure EL1 Interrupt : 0000001D [034h 0052 4] EL1 Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 Always On : 0
[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E @@ -37,25 +37,28 @@
[040h 0064 4] Virtual Timer Interrupt : 0000001B [044h 0068 4] VT Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 Always On : 0
[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A [04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 Trigger Mode : 0 Polarity : 0 Always On : 0 [050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF
[058h 0088 4] Platform Timer Count : 00000000 [05Ch 0092 4] Platform Timer Offset : 00000000 +[060h 0096 4] Virtual EL2 Timer GSIV : 00000000 +[064h 0100 4] Virtual EL2 Timer Flags : 00000000
-Raw Table Data: Length 96 (0x60) +Raw Table Data: Length 104 (0x68)
- 0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20 // GTDT`.....BOCHS + 0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20 // GTDTh.....BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC 0020: 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00 // ................ 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................ 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................ 0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 // ........
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Ard Biesheuvel <ardb@kernel.org> Message-id: 20240122143537.233498-4-peter.maydell@linaro.org
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