Revision tags: v8.0.0 |
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94901422 |
| 07-Apr-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/s390x: Simplify constraints on qemu_ld/st
Adjust the softmmu tlb to use R0+R1, not any of the normally available registers. Since we handle overlap betwen inputs and helper arguments, we can al
tcg/s390x: Simplify constraints on qemu_ld/st
Adjust the softmmu tlb to use R0+R1, not any of the normally available registers. Since we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.2.0 |
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4134083f |
| 08-Dec-2022 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/s390x: Tighten constraints for and_i64
Let the register allocator handle such immediates by matching only what one insn can achieve.
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off
tcg/s390x: Tighten constraints for and_i64
Let the register allocator handle such immediates by matching only what one insn can achieve.
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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b2509acc |
| 08-Dec-2022 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/s390x: Tighten constraints for or_i64 and xor_i64
Drop support for sequential OR and XOR, as the serial dependency is slower than loading the constant first. Let the register allocator handle s
tcg/s390x: Tighten constraints for or_i64 and xor_i64
Drop support for sequential OR and XOR, as the serial dependency is slower than loading the constant first. Let the register allocator handle such immediates by matching only what one insn can achieve.
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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4143f78d |
| 10-Oct-2022 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/s390x: Use register pair allocation for div and mulu2
Previously we hard-coded R2 and R3.
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@l
tcg/s390x: Use register pair allocation for div and mulu2
Previously we hard-coded R2 and R3.
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.0.0, v6.2.0, v6.1.0, v5.2.0 |
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34ef7676 |
| 14-Sep-2020 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/s390x: Add host vector framework
Add registers and function stubs. The functionality is disabled via squashing s390_facilities[2] to 0.
We must still include results for the mandatory opcodes
tcg/s390x: Add host vector framework
Add registers and function stubs. The functionality is disabled via squashing s390_facilities[2] to 0.
We must still include results for the mandatory opcodes in tcg_target_op_def, as all opcodes are checked during tcg init.
Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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3704993f |
| 14-Sep-2020 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/s390x: Rename from tcg/s390
This emphasizes that we don't support s390, only 64-bit s390x hosts.
Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org
tcg/s390x: Rename from tcg/s390
This emphasizes that we don't support s390, only 64-bit s390x hosts.
Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: David Hildenbrand <david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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