| 3213da7b | 05-Oct-2024 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/ppc: Use TCG_REG_TMP2 for scratch index in prepare_host_addr
In tcg_out_qemu_ldst_i128, we need a non-zero index register,
which we then use as a base register in several address modes.
Since we
tcg/ppc: Use TCG_REG_TMP2 for scratch index in prepare_host_addr
In tcg_out_qemu_ldst_i128, we need a non-zero index register,
which we then use as a base register in several address modes.
Since we always have TCG_REG_TMP2 available, use that.
Cc: qemu-stable@nongnu.org
Fixes: 526cd4ec01f ("tcg/ppc: Support 128-bit load/store")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2597
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-By: Michael Tokarev <mjt@tls.msk.ru>
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| ce8e5f2f | 10-Sep-2024 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/ppc: Optimize cmpsel with constant 0/-1 arguments
These can be simplified to and/or/andc/orc,
avoiding the load of the constantinto a register.
Signed-off-by: Richard Henderson <richard.henders
tcg/ppc: Optimize cmpsel with constant 0/-1 arguments
These can be simplified to and/or/andc/orc,
avoiding the load of the constantinto a register.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| 282ef7e8 | 27-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/ppc: Add TCG_CT_CONST_CMP
Better constraint for tcg_out_cmp, based on the comparison.
We can't yet remove the fallback to load constants into a
scratch because of tcg_out_cmp2, but that path sho
tcg/ppc: Add TCG_CT_CONST_CMP
Better constraint for tcg_out_cmp, based on the comparison.
We can't yet remove the fallback to load constants into a
scratch because of tcg_out_cmp2, but that path should not
be as frequent.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| 740f1d40 | 24-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel
Using cr0 means we could choose to use rc=1 to compute the condition.
Adjust the tables and tcg_out_cmp that feeds them.
Reviewed-by: Philippe Mathieu-
tcg/ppc: Use cr0 in tcg_to_bc and tcg_to_isel
Using cr0 means we could choose to use rc=1 to compute the condition.
Adjust the tables and tcg_out_cmp that feeds them.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| 1f8e4dc1 | 04-Aug-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/ppc: Use prefixed instructions in tcg_out_mem_long
When the offset is out of range of the non-prefixed insn, but
fits the 34-bit immediate of the prefixed insn, use that.
Reviewed-by: Jordan Ni
tcg/ppc: Use prefixed instructions in tcg_out_mem_long
When the offset is out of range of the non-prefixed insn, but
fits the 34-bit immediate of the prefixed insn, use that.
Reviewed-by: Jordan Niethe <jniethe5@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| 103044e4 | 26-Jun-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/ppc: Use PADDI in tcg_out_movi
PADDI can load 34-bit immediates and 34-bit pc-relative addresses.
Reviewed-by: Jordan Niethe <jniethe5@gmail.com>
Signed-off-by: Richard Henderson <richard.hende
tcg/ppc: Use PADDI in tcg_out_movi
PADDI can load 34-bit immediates and 34-bit pc-relative addresses.
Reviewed-by: Jordan Niethe <jniethe5@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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