| 2cff741d | 25-Oct-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/mips: Always implement movcond
Expand as branch over move if not supported in the ISA.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231026041404.1229328-3-rich
tcg/mips: Always implement movcond
Expand as branch over move if not supported in the ISA.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20231026041404.1229328-3-richard.henderson@linaro.org>
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| b56d5a8a | 17-May-2023 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN
Since e03b56863d2b, which replaced HOST_WORDS_BIGENDIAN
with HOST_BIG_ENDIAN, there is no need to define a second
symbol which is [0,1].
Reviewed-by:
tcg/mips: Replace MIPS_BE with HOST_BIG_ENDIAN
Since e03b56863d2b, which replaced HOST_WORDS_BIGENDIAN
with HOST_BIG_ENDIAN, there is no need to define a second
symbol which is [0,1].
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| 269e93ab | 06-Aug-2021 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/mips: Try three insns with shift and add in tcg_out_movi
These sequences are inexpensive to test. Maxing out at three insns
results in the same space as a load plus the constant pool entry.
Si
tcg/mips: Try three insns with shift and add in tcg_out_movi
These sequences are inexpensive to test. Maxing out at three insns
results in the same space as a load plus the constant pool entry.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| 1d159e64 | 06-Aug-2021 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/mips: Try tb-relative addresses in tcg_out_movi
These addresses are often loaded by the qemu_ld/st slow path,
for loading the retaddr value.
Signed-off-by: Richard Henderson <richard.henderson@
tcg/mips: Try tb-relative addresses in tcg_out_movi
These addresses are often loaded by the qemu_ld/st slow path,
for loading the retaddr value.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| 4316de32 | 06-Aug-2021 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/mips: Aggressively use the constant pool for n64 calls
Repeated calls to a single helper are common -- especially
the ones for softmmu memory access. Prefer the constant pool
to longer sequence
tcg/mips: Aggressively use the constant pool for n64 calls
Repeated calls to a single helper are common -- especially
the ones for softmmu memory access. Prefer the constant pool
to longer sequences to increase sharing.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| 48c12ba7 | 06-Aug-2021 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/mips: Use the constant pool for 64-bit constants
During normal processing, the constant pool is accessible via
TCG_REG_TB. During the prologue, it is accessible via TCG_REG_T9.
Signed-off-by:
tcg/mips: Use the constant pool for 64-bit constants
During normal processing, the constant pool is accessible via
TCG_REG_TB. During the prologue, it is accessible via TCG_REG_T9.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| 47a57286 | 06-Aug-2021 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/mips: Split out tcg_out_movi_one
Emit all constants that can be loaded in exactly one insn.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.hen
tcg/mips: Split out tcg_out_movi_one
Emit all constants that can be loaded in exactly one insn.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
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