| #
6f398e53 |
| 05-Jun-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210604' into staging
Host vector support for arm neon.
# gpg: Signature made Fri 04 Jun 2021 19:56:59 BST
# gpg:
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210604' into staging
Host vector support for arm neon.
# gpg: Signature made Fri 04 Jun 2021 19:56:59 BST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth-gitlab/tags/pull-tcg-20210604:
tcg/arm: Implement TCG_TARGET_HAS_rotv_vec
tcg/arm: Implement TCG_TARGET_HAS_roti_vec
tcg/arm: Implement TCG_TARGET_HAS_shv_vec
tcg/arm: Implement TCG_TARGET_HAS_bitsel_vec
tcg/arm: Implement TCG_TARGET_HAS_minmax_vec
tcg/arm: Implement TCG_TARGET_HAS_sat_vec
tcg/arm: Implement TCG_TARGET_HAS_mul_vec
tcg/arm: Implement TCG_TARGET_HAS_shi_vec
tcg/arm: Implement andc, orc, abs, neg, not vector operations
tcg/arm: Implement minimal vector operations
tcg/arm: Implement tcg_out_dup*_vec
tcg/arm: Implement tcg_out_mov for vector types
tcg/arm: Implement tcg_out_ld/st for vector types
tcg/arm: Add host vector framework
tcg: Change parameters for tcg_target_const_match
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
| #
5047ae64 |
| 05-Sep-2020 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/arm: Implement TCG_TARGET_HAS_roti_vec
Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec.
For NEON, this is shift-right followed by shift-left-and-insert.
tcg/arm: Implement TCG_TARGET_HAS_roti_vec
Implement via expansion, so don't actually set TCG_TARGET_HAS_roti_vec.
For NEON, this is shift-right followed by shift-left-and-insert.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
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| #
31d36639 |
| 05-Sep-2020 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/arm: Implement TCG_TARGET_HAS_shv_vec
The three vector shift by vector operations are all implemented via
expansion. Therefore do not actually set TCG_TARGET_HAS_shv_vec,
as non
tcg/arm: Implement TCG_TARGET_HAS_shv_vec
The three vector shift by vector operations are all implemented via
expansion. Therefore do not actually set TCG_TARGET_HAS_shv_vec,
as none of shlv_vec, shrv_vec, sarv_vec may actually appear in the
instruction stream, and therefore also do not appear in tcg_target_op_def.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
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| #
000cf477 |
| 03-May-2021 |
Richard Henderson <richard.henderson@linaro.org> |
tcg/arm: Add host vector framework
Add registers and function stubs. The functionality
is disabled via use_neon_instructions defined to 0.
We must still include results for the
tcg/arm: Add host vector framework
Add registers and function stubs. The functionality
is disabled via use_neon_instructions defined to 0.
We must still include results for the mandatory opcodes in
tcg_target_op_def, as all opcodes are checked during tcg init.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
show more ...
|