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378e43fa |
| 07-Mar-2023 |
Philipp Tomsich <philipp.tomsich@vrull.eu> |
target/riscv: refactor Zicond support
After the original Zicond support was stuck/fell through the cracks on the mailing list at v3 (and a different implementation was merged in the meanwhile), we n
target/riscv: refactor Zicond support
After the original Zicond support was stuck/fell through the cracks on the mailing list at v3 (and a different implementation was merged in the meanwhile), we need to refactor Zicond to prepare it to be reused by XVentanaCondOps.
This commit lifts the common logic out into gen_czero and uses this via gen_logic and 2 helper functions (effectively partial closures).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307180708.302867-2-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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b8e1f32c |
| 21-Feb-2023 |
Weiwei Li <liweiwei@iscas.ac.cn> |
target/riscv: Add support for Zicond extension
The spec can be found in https://github.com/riscv/riscv-zicond. Two instructions are added: - czero.eqz: Moves zero to a register rd, if the condition
target/riscv: Add support for Zicond extension
The spec can be found in https://github.com/riscv/riscv-zicond. Two instructions are added: - czero.eqz: Moves zero to a register rd, if the condition rs2 is equal to zero, otherwise moves rs1 to rd. - czero.nez: Moves zero to a register rd, if the condition rs2 is nonzero, otherwise moves rs1 to rd.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-ID: <20230221091009.36545-1-liweiwei@iscas.ac.cn> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
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