target/ppc : Update VSX storage access insns to use tcg_gen_qemu _ld/st_i128.

Updated many VSX instructions to use tcg_gen_qemu_ld/st_i128, instead of using
tcg_gen_qemu_ld/st_i64 consecutively.
Int

target/ppc : Update VSX storage access insns to use tcg_gen_qemu _ld/st_i128.

Updated many VSX instructions to use tcg_gen_qemu_ld/st_i128, instead of using
tcg_gen_qemu_ld/st_i64 consecutively.
Introduced functions {get,set}_vsr_full to facilitate the above & for future use.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Update VMX storage access insns to use tcg_gen_qemu_ld/st_i128.

Updated instructions {l, st}vx to use tcg_gen_qemu_ld/st_i128,
instead of using 64 bits loads/stores in succession.
Introd

target/ppc: Update VMX storage access insns to use tcg_gen_qemu_ld/st_i128.

Updated instructions {l, st}vx to use tcg_gen_qemu_ld/st_i128,
instead of using 64 bits loads/stores in succession.
Introduced functions {get, set}_avr_full in vmx-impl.c.inc to
facilitate the above, and potential future usage.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Move get/set_avr64 functions to vmx-impl.c.inc.

Those functions are used to ld/st data to and from Altivec registers,
in 64 bits chunks, and are only used in vmx-impl.c.inc file,
hence t

target/ppc: Move get/set_avr64 functions to vmx-impl.c.inc.

Those functions are used to ld/st data to and from Altivec registers,
in 64 bits chunks, and are only used in vmx-impl.c.inc file,
hence the clean-up movement.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Move VSX fp compare insns to decodetree.

Moving the following instructions to decodetree specification:

xvcmp{eq, gt, ge, ne}{s, d}p : XX3-form

The changes were verified by validating

target/ppc: Move VSX fp compare insns to decodetree.

Moving the following instructions to decodetree specification:

xvcmp{eq, gt, ge, ne}{s, d}p : XX3-form

The changes were verified by validating that the tcg-ops generated for those
instructions remain the same which were captured using the '-d in_asm,op' flag.

Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Move VSX vector storage access insns to decodetree.

Moving the following instructions to decodetree specification:

lxv{b16, d2, h8, w4, ds, ws}x : X-form
stxv{b16, d2, h8, w4}x

target/ppc: Move VSX vector storage access insns to decodetree.

Moving the following instructions to decodetree specification:

lxv{b16, d2, h8, w4, ds, ws}x : X-form
stxv{b16, d2, h8, w4}x : X-form

The changes were verified by validating that the tcg-ops generated for those
instructions remain the same, which were captured using the '-d in_asm,op' flag.

Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Move VSX vector with length storage access insns to decodetree.

Moving the following instructions to decodetree specification :

{l, st}xvl(l) : X-form

The changes wer

target/ppc: Move VSX vector with length storage access insns to decodetree.

Moving the following instructions to decodetree specification :

{l, st}xvl(l) : X-form

The changes were verified by validating that the tcg-ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.

Also added a new function do_ea_calc_ra to calculate the effective address :
EA <- (RA == 0) ? 0 : GPR[RA], which is now used by the above-said insns,
and shall be used later by (p){lx, stx}vp insns.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
[np: Fix 32-bit build]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Moving VSX scalar storage access insns to decodetree.

Moving the following instructions to decodetree specification :

lxs{d, iwa, ibz, ihz, iwz, sp}x : X-form
stxs{d, ib, ih, iw, sp}

target/ppc: Moving VSX scalar storage access insns to decodetree.

Moving the following instructions to decodetree specification :

lxs{d, iwa, ibz, ihz, iwz, sp}x : X-form
stxs{d, ib, ih, iw, sp}x : X-form

The changes were verified by validating that the tcg-ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.

Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Move VSX logical instructions to decodetree.

Moving the following instructions to decodetree specification :

xxl{and, andc, or, orc, nor, xor, nand, eqv} : XX3-form

The changes were v

target/ppc: Move VSX logical instructions to decodetree.

Moving the following instructions to decodetree specification :

xxl{and, andc, or, orc, nor, xor, nand, eqv} : XX3-form

The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.

Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Move VSX arithmetic and max/min insns to decodetree.

Moving the following instructions to decodetree specification:

x{s, v}{add, sub, mul, div}{s, d}p : XX3-form
xs{max, min}dp, xv{ma

target/ppc: Move VSX arithmetic and max/min insns to decodetree.

Moving the following instructions to decodetree specification:

x{s, v}{add, sub, mul, div}{s, d}p : XX3-form
xs{max, min}dp, xv{max, min}{s, d}p : XX3-form

The changes were verfied by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.

Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Move ISA300 flag check out of do_helper_XX3.

Moving PPC2_ISA300 flag check out of do_helper_XX3 method in vmx-impl.c.inc
so that the helper can be used with other instructions as well.

target/ppc: Move ISA300 flag check out of do_helper_XX3.

Moving PPC2_ISA300 flag check out of do_helper_XX3 method in vmx-impl.c.inc
so that the helper can be used with other instructions as well.

Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Improve VMX integer add/sub saturate instructions.

No need for a full comparison; xor produces non-zero bits for QC just fine.

Suggested-by: Richard Henderson <richard.henderson@linaro.

target/ppc: Improve VMX integer add/sub saturate instructions.

No need for a full comparison; xor produces non-zero bits for QC just fine.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rath.chinmay@linux.ibm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

show more ...

target/ppc: Move VMX integer add/sub saturate insns to decodetree.

Moving the following instructions to decodetree specification :

v{add,sub}{u,s}{b,h,w}s : VX-form

The changes were verified by

target/ppc: Move VMX integer add/sub saturate insns to decodetree.

Moving the following instructions to decodetree specification :

v{add,sub}{u,s}{b,h,w}s : VX-form

The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: add SMT support to msgsnd broadcast

msgsnd has a broadcast mode that sends hypervisor doorbells to all
threads belonging to the same core as the target. A "subcore" mode
sends to all or

target/ppc: add SMT support to msgsnd broadcast

msgsnd has a broadcast mode that sends hypervisor doorbells to all
threads belonging to the same core as the target. A "subcore" mode
sends to all or one thread depending on 1LPAR mode.

Reviewed-by: Glenn Miles <milesg@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Implement attn instruction on BookS 64-bit processors

attn is an implementation-specific instruction that on POWER (and G5/
970) can be enabled with a HID bit (disabled = illegal), and e

target/ppc: Implement attn instruction on BookS 64-bit processors

attn is an implementation-specific instruction that on POWER (and G5/
970) can be enabled with a HID bit (disabled = illegal), and executing
it causes the host processor to stop and the service processor to be
notified. Generally used for debugging.

Implement attn and make it checkstop the system, which should be good
enough for QEMU debugging.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Add clrbhrb and mfbhrbe instructions

Add support for the clrbhrb and mfbhrbe instructions.

Since neither instruction is believed to be critical to
performance, both instructions were im

target/ppc: Add clrbhrb and mfbhrbe instructions

Add support for the clrbhrb and mfbhrbe instructions.

Since neither instruction is believed to be critical to
performance, both instructions were implemented using helper
functions.

Access to both instructions is controlled by bits in the
HFSCR (for privileged state) and MMCR0 (for problem state).
A new function, helper_mmcr0_facility_check, was added for
checking MMCR0[BHRBA] and raising a facility_unavailable exception
if required.

NOTE: For P8 and P9, due to a performance issue, branch history will
not be kept, but the instructions will be allowed to execute
as normal with the exception that the mfbhrbe instruction will
always return a zero value.

Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Add recording of taken branches to BHRB

This commit continues adding support for the Branch History
Rolling Buffer (BHRB) as is provided starting with the P8
processor and continuing wit

target/ppc: Add recording of taken branches to BHRB

This commit continues adding support for the Branch History
Rolling Buffer (BHRB) as is provided starting with the P8
processor and continuing with its successors. This commit
is limited to the recording and filtering of taken branches.

The following changes were made:

- Enabled functionality on P10 processors only due to
performance impact seen with P8 and P9 where it is not
disabled for non problem state branches.
- Added a BHRB buffer for storing branch instruction and
target addresses for taken branches
- Renamed gen_update_cfar to gen_update_branch_history and
added a 'target' parameter to hold the branch target
address and 'inst_type' parameter to use for filtering
- Added TCG code to gen_update_branch_history that stores
data to the BHRB and updates the BHRB offset.
- Added BHRB resource initialization and reset functions

Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Move VMX integer max/min instructions to decodetree.

Moving the following instructions to decodetree specification :

v{max, min}{u, s}{b, h, w, d} : VX-form

The changes were verified

target/ppc: Move VMX integer max/min instructions to decodetree.

Moving the following instructions to decodetree specification :

v{max, min}{u, s}{b, h, w, d} : VX-form

The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

show more ...

target/ppc: Move VMX integer logical instructions to decodetree.

Moving the following instructions to decodetree specification:

v{and, andc, nand, or, orc, nor, xor, eqv} : VX-form

The changes we

target/ppc: Move VMX integer logical instructions to decodetree.

Moving the following instructions to decodetree specification:

v{and, andc, nand, or, orc, nor, xor, eqv} : VX-form

The changes were verified by validating that the tcp ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

show more ...

target/ppc: Move VMX storage access instructions to decodetree

Moving the following instructions to decodetree specification :

{l,st}ve{b,h,w}x,
{l,st}v{x,xl},
lvs{l,r} : X-form

The changes we

target/ppc: Move VMX storage access instructions to decodetree

Moving the following instructions to decodetree specification :

{l,st}ve{b,h,w}x,
{l,st}v{x,xl},
lvs{l,r} : X-form

The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

show more ...

target/ppc: Move logical fixed-point instructions to decodetree.

Moving the below instructions to decodetree specification :

andi[s]., {ori, xori}[s] : D-form

{and, andc, nand, or, orc, nor, x

target/ppc: Move logical fixed-point instructions to decodetree.

Moving the below instructions to decodetree specification :

andi[s]., {ori, xori}[s] : D-form

{and, andc, nand, or, orc, nor, xor, eqv}[.],
exts{b, h, w}[.], cnt{l, t}z{w, d}[.],
popcnt{b, w, d}, prty{w, d}, cmp, bpermd : X-form

With this patch, all the fixed-point logical instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Move cmp{rb, eqb}, tw[i], td[i], isel instructions to decodetree.

Moving the following instructions to decodetree specification :

cmp{rb, eqb}, t{w, d} : X-form
t{w, d}i : D-form
is

target/ppc: Move cmp{rb, eqb}, tw[i], td[i], isel instructions to decodetree.

Moving the following instructions to decodetree specification :

cmp{rb, eqb}, t{w, d} : X-form
t{w, d}i : D-form
isel : A-form

The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Also for CMPRB, following review comments :
Replaced repetition of arithmetic right shifting (tcg_gen_shri_i32) followed
by extraction of last 8 bits (tcg_gen_ext8u_i32) with extraction of the required
bits using offsets (tcg_gen_extract_i32).

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Move div/mod fixed-point insns (64 bits operands) to decodetree.

Moving the below instructions to decodetree specification :

divd[u, e, eu][o][.] : XO-form
mod{sd, ud} : X-form

With

target/ppc: Move div/mod fixed-point insns (64 bits operands) to decodetree.

Moving the below instructions to decodetree specification :

divd[u, e, eu][o][.] : XO-form
mod{sd, ud} : X-form

With this patch, all the fixed-point arithmetic instructions have been
moved to decodetree.
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured using the '-d in_asm,op' flag.
Also, remaned do_divwe method in fixedpoint-impl.c.inc to do_dive because it is
now used to divide doubleword operands as well, and not just words.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Move multiply fixed-point insns (64-bit operands) to decodetree.

Moving the following instructions to decodetree :

mul{ld, ldo, hd, hdu}[.] : XO-form
madd{hd, hdu, ld} : VA-form

The

target/ppc: Move multiply fixed-point insns (64-bit operands) to decodetree.

Moving the following instructions to decodetree :

mul{ld, ldo, hd, hdu}[.] : XO-form
madd{hd, hdu, ld} : VA-form

The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op'
flag.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

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target/ppc: Move neg, darn, mod{sw, uw} to decodetree.

Moving the below instructions to decodetree specification :

neg[o][.] : XO-form
mod{sw, uw}, darn : X-form

The changes were verified

target/ppc: Move neg, darn, mod{sw, uw} to decodetree.

Moving the below instructions to decodetree specification :

neg[o][.] : XO-form
mod{sw, uw}, darn : X-form

The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
[np: 32-bit compile fix]
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

show more ...

target/ppc: Move divw[u, e, eu] instructions to decodetree.

Moving the following instructions to decodetree specification :
divw[u, e, eu][o][.] : XO-form

The changes were verified by validating

target/ppc: Move divw[u, e, eu] instructions to decodetree.

Moving the following instructions to decodetree specification :
divw[u, e, eu][o][.] : XO-form

The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Chinmay Rath <rathc@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>

show more ...