#
597f9b2d |
| 28-Jan-2023 |
Richard Henderson <richard.henderson@linaro.org> |
accel/tcg: Pass max_insn to gen_intermediate_code by pointer
In preparation for returning the number of insns generated via the same pointer. Adjust only the prototypes so far.
Reviewed-by: Philip
accel/tcg: Pass max_insn to gen_intermediate_code by pointer
In preparation for returning the number of insns generated via the same pointer. Adjust only the prototypes so far.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.2.0 |
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#
59f8c04b |
| 27-Oct-2022 |
Helge Deller <deller@gmx.de> |
target/hppa: Fix fid instruction emulation
The fid instruction (Floating-Point Identify) puts the FPU model and revision into the Status Register. Since those values shouldn't be 0, store values the
target/hppa: Fix fid instruction emulation
The fid instruction (Floating-Point Identify) puts the FPU model and revision into the Status Register. Since those values shouldn't be 0, store values there which a PCX-L2 (for 32-bit) or a PCX-W2 (for 64-bit) would return. Noticed while trying to install MPE/iX.
Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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#
0786a3b6 |
| 28-Sep-2022 |
Helge Deller <deller@gmx.de> |
target/hppa: Generate illegal instruction exception for 64-bit instructions
Qemu currently emulates a 32-bit CPU only, and crashes with this error when it faces a 64-bit load (e.g. "ldd 0(r26),r0")
target/hppa: Generate illegal instruction exception for 64-bit instructions
Qemu currently emulates a 32-bit CPU only, and crashes with this error when it faces a 64-bit load (e.g. "ldd 0(r26),r0") or a 64-bit store (e.g. "std r26,0(r26)") instruction in the guest:
ERROR:../qemu/tcg/tcg-op.c:2822:tcg_canonicalize_memop: code should not be reached
Add checks for 64-bit sizes and generate an illegal instruction exception if necessary.
Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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#
e9cc3aca |
| 24-Oct-2022 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Convert to tcg_ops restore_state_to_opc
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
306c8721 |
| 11-Aug-2022 |
Richard Henderson <richard.henderson@linaro.org> |
accel/tcg: Add pc and host_pc params to gen_intermediate_code
Pass these along to translator_loop -- pc may be used instead of tb->pc, and host_pc is currently unused. Adjust all targets at one tim
accel/tcg: Add pc and host_pc params to gen_intermediate_code
Pass these along to translator_loop -- pc may be used instead of tb->pc, and host_pc is currently unused. Adjust all targets at one time.
Acked-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Tested-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v7.0.0 |
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#
8eb806a7 |
| 17-Apr-2022 |
Richard Henderson <richard.henderson@linaro.org> |
exec/translator: Pass the locked filepointer to disas_log hook
We have fetched and locked the logfile in translator_loop. Pass the filepointer down to the disas_log hook so that it need not be fetch
exec/translator: Pass the locked filepointer to disas_log hook
We have fetched and locked the logfile in translator_loop. Pass the filepointer down to the disas_log hook so that it need not be fetched and locked again.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220417183019.755276-13-richard.henderson@linaro.org>
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#
e03b5686 |
| 23-Mar-2022 |
Marc-André Lureau <marcandre.lureau@redhat.com> |
Replace config-time define HOST_WORDS_BIGENDIAN
Replace a config-time define with a compile time condition define (compatible with clang and gcc) that must be declared prior to its usage. This avoid
Replace config-time define HOST_WORDS_BIGENDIAN
Replace a config-time define with a compile time condition define (compatible with clang and gcc) that must be declared prior to its usage. This avoids having a global configure time define, but also prevents from bad usage, if the config header wasn't included before.
This can help to make some code independent from qemu too.
gcc supports __BYTE_ORDER__ from about 4.6 and clang from 3.2.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> [ For the s390x parts I'm involved in ] Acked-by: Halil Pasic <pasic@linux.ibm.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220323155743.1585078-7-marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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#
4a4554c6 |
| 05-Jan-2022 |
Helge Deller <deller@gmx.de> |
hppa: Add support for an emulated TOC/NMI button.
Almost all PA-RISC machines have either a button that is labeled with 'TOC' or a BMC/GSP function to trigger a TOC. TOC is a non-maskable interrupt
hppa: Add support for an emulated TOC/NMI button.
Almost all PA-RISC machines have either a button that is labeled with 'TOC' or a BMC/GSP function to trigger a TOC. TOC is a non-maskable interrupt that is sent to the processor. This can be used for diagnostic purposes like obtaining a stack trace/register dump or to enter KDB/KGDB in Linux.
This patch adds support for such an emulated TOC button.
It wires up the qemu monitor "nmi" command to trigger a TOC. For that it provides the hppa_nmi function which is assigned to the nmi_monitor_handler function pointer. When called it raises the EXCP_TOC hardware interrupt in the hppa_cpu_do_interrupt() function. The interrupt function then calls the architecturally defined TOC function in SeaBIOS-hppa firmware (at fixed address 0xf0000000).
According to the PA-RISC PDC specification, the SeaBIOS firmware then writes the CPU registers into PIM (processor internal memmory) for later analysis. In order to write all registers it needs to know the contents of the CPU "shadow registers" and the IASQ- and IAOQ-back values. The IAOQ/IASQ values are provided by qemu in shadow registers when entering the SeaBIOS TOC function. This patch adds a new aritificial opcode "getshadowregs" (0xfffdead2) which restores the original values of the shadow registers. With this opcode SeaBIOS can store those registers as well into PIM before calling an OS-provided TOC handler.
To trigger a TOC, switch to the qemu monitor with Ctrl-A C, and type in the command "nmi". After the TOC started the OS-debugger, exit the qemu monitor with Ctrl-A C.
Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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#
fc313c64 |
| 06-Jan-2022 |
Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> |
exec/memop: Adding signedness to quad definitions
Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit
exec/memop: Adding signedness to quad definitions
Renaming defines for quad in their various forms so that their signedness is now explicit. Done using git grep as suggested by Philippe, with a bit of hand edition to keep assignments aligned.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-2-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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#
217d1a5e |
| 27-Dec-2021 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Implement prctl_unalign_sigbus
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap.
Signed-o
target/hppa: Implement prctl_unalign_sigbus
Leave TARGET_ALIGNED_ONLY set, but use the new CPUState flag to set MO_UNALN for the instructions that the kernel handles in the unaligned trap.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20211227150127.2659293-6-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
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Revision tags: v6.2.0 |
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#
05bfd4db |
| 13-Dec-2021 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Fix deposit assert from trans_shrpw_imm
Because sa may be 0,
tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa);
may attempt a zero-width deposit at bit 32, which will asse
target/hppa: Fix deposit assert from trans_shrpw_imm
Because sa may be 0,
tcg_gen_deposit_reg(dest, t0, cpu_gr[a->r1], 32 - sa, sa);
may attempt a zero-width deposit at bit 32, which will assert for TARGET_REGISTER_BITS == 32.
Use the newer extract2 when possible, which itself includes the rotri special case; otherwise mirror the code from trans_shrpw_sar, using concat and shri.
Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/635 Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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Revision tags: v6.1.0 |
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#
8532a14e |
| 19-Jul-2021 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Drop checks for singlestep_enabled
GDB single-stepping is now handled generically.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.hende
target/hppa: Drop checks for singlestep_enabled
GDB single-stepping is now handled generically.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
57d49416 |
| 16-Aug-2021 |
Bin Meng <bmeng.cn@gmail.com> |
tcg: Remove tcg_global_reg_new defines
Since commit 1c2adb958fc0 ("tcg: Initialize cpu_env generically"), these tcg_global_reg_new_ macros are not used anywhere.
Signed-off-by: Bin Meng <bmeng.cn@g
tcg: Remove tcg_global_reg_new defines
Since commit 1c2adb958fc0 ("tcg: Initialize cpu_env generically"), these tcg_global_reg_new_ macros are not used anywhere.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210816143507.11200-1-bmeng.cn@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
4e116893 |
| 09-Aug-2021 |
Ilya Leoshkevich <iii@linux.ibm.com> |
accel/tcg: Add DisasContextBase argument to translator_ld*
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> [rth: Split out of a larger patch.] Signed-off-by: Richard Henderson <richard.henderson
accel/tcg: Add DisasContextBase argument to translator_ld*
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com> [rth: Split out of a larger patch.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
1d6f147f |
| 26-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20210725' into staging The Hexagon target was silently failing the SIGSEGV test because the signal handler was not called.
Merge remote-tracking branch 'remotes/quic/tags/pull-hex-20210725' into staging The Hexagon target was silently failing the SIGSEGV test because the signal handler was not called. Patch 1/2 fixes the Hexagon target Patch 2/2 drops include qemu.h from target/hexagon/op_helper.c **** Changes in v2 **** Drop changes to linux-test.c due to intermittent failures on riscv # gpg: Signature made Sun 25 Jul 2021 22:39:38 BST # gpg: using RSA key 7B0244FB12DE4422 # gpg: Good signature from "Taylor Simpson (Rock on) <tsimpson@quicinc.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 3635 C788 CE62 B91F D4C5 9AB4 7B02 44FB 12DE 4422 * remotes/quic/tags/pull-hex-20210725: target/hexagon: Drop include of qemu.h Hexagon (target/hexagon) remove put_user_*/get_user_* Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
a146af86 |
| 23-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/kraxel/tags/vga-20210723-pull-request' into staging vga: fixes for qxl and virtio-gpu # gpg: Signature made Fri 23 Jul 2021 06:54:34 BST #
Merge remote-tracking branch 'remotes/kraxel/tags/vga-20210723-pull-request' into staging vga: fixes for qxl and virtio-gpu # gpg: Signature made Fri 23 Jul 2021 06:54:34 BST # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/vga-20210723-pull-request: hw/display: fix virgl reset regression vl: add virtio-vga-gl to the default_list hw/display: fail early when multiple virgl devices are requested Revert "qxl: add migration blocker to avoid pre-save assert" qxl: remove assert in qxl_pre_save. hw/display/virtio-gpu: Fix memory leak (CID 1453811) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
7b7ca8eb |
| 22-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging Bugfixes. # gpg: Signature made Thu 22 Jul 2021 14:11:27 BST # gpg: using RSA
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging Bugfixes. # gpg: Signature made Thu 22 Jul 2021 14:11:27 BST # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini-gitlab/tags/for-upstream: configure: Let --without-default-features disable vhost-kernel and vhost-vdpa configure: Fix the default setting of the "xen" feature configure: Allow vnc to get disabled with --without-default-features configure: Fix --without-default-features propagation to meson meson: fix dependencies for modinfo configure: Drop obsolete check for the alloc_size attribute target/i386: Added consistency checks for EFER target/i386: Added consistency checks for CR4 target/i386: Added V_INTR_PRIO check to virtual interrupts qemu-config: restore "machine" in qmp_query_command_line_options() usb: fix usb-host dependency check chardev-spice: add missing module_obj directive vl: Parse legacy default_machine_opts qemu-config: fix memory leak on ferror() qemu-config: never call the callback after an error, fix leak Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
beb19138 |
| 22-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210721' into staging Atomic build fixes for clang-12 Breakpoint reorg # gpg: Signature made Wed 21 Jul 2021 20:5
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210721' into staging Atomic build fixes for clang-12 Breakpoint reorg # gpg: Signature made Wed 21 Jul 2021 20:57:50 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210721: (27 commits) accel/tcg: Record singlestep_enabled in tb->cflags accel/tcg: Hoist tb_cflags to a local in translator_loop accel/tcg: Remove TranslatorOps.breakpoint_check accel/tcg: Move breakpoint recognition outside translation accel/tcg: Merge tb_find into its only caller target/avr: Implement gdb_adjust_breakpoint hw/core: Introduce CPUClass.gdb_adjust_breakpoint target/i386: Implement debug_check_breakpoint target/arm: Implement debug_check_breakpoint hw/core: Introduce TCGCPUOps.debug_check_breakpoint accel/tcg: Use CF_NO_GOTO_{TB, PTR} in cpu_exec_step_atomic accel/tcg: Handle -singlestep in curr_cflags accel/tcg: Drop CF_NO_GOTO_PTR from -d nochain accel/tcg: Add CF_NO_GOTO_TB and CF_NO_GOTO_PTR target/alpha: Drop goto_tb path in gen_call_pal accel/tcg: Move curr_cflags into cpu-exec.c accel/tcg: Reduce CF_COUNT_MASK to match TCG_MAX_INSNS accel/tcg: Push trace info building into atomic_common.c.inc trace: Fold mem-internal.h into mem.h accel/tcg: Expand ATOMIC_MMU_LOOKUP_* ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
b5cf7428 |
| 19-Jul-2021 |
Richard Henderson <richard.henderson@linaro.org> |
accel/tcg: Remove TranslatorOps.breakpoint_check The hook is now unused, with breakpoints checked outside translation. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
accel/tcg: Remove TranslatorOps.breakpoint_check The hook is now unused, with breakpoints checked outside translation. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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#
d4127349 |
| 15-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/berrange-gitlab/tags/crypto-and-more-pull-request' into staging Merge crypto updates and misc fixes * Introduce a GNUTLS backend for crypto al
Merge remote-tracking branch 'remotes/berrange-gitlab/tags/crypto-and-more-pull-request' into staging Merge crypto updates and misc fixes * Introduce a GNUTLS backend for crypto algorithms * Change crypto library preference gnutls > gcrypt > nettle > built-in * Remove built-in DES impl * Remove XTS mode from built-in AES impl * Fix seccomp rules to allow resource info getters * Fix migration performance test * Use GDateTime in io/ and net/rocker/ code * Improve docs for -smp # gpg: Signature made Wed 14 Jul 2021 15:08:00 BST # gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full] # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" [full] # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange-gitlab/tags/crypto-and-more-pull-request: (26 commits) qemu-options: rewrite help for -smp options qemu-options: tweak to show that CPU count is optional qemu-options: re-arrange CPU topology options docs: fix typo s/Intel/AMD/ in CPU model notes tests/migration: fix unix socket migration seccomp: don't block getters for resource control syscalls io: use GDateTime for formatting timestamp for websock headers net/rocker: use GDateTime for formatting timestamp in debug messages crypto: prefer gnutls as the crypto backend if new enough crypto: add gnutls pbkdf provider crypto: add gnutls hmac provider crypto: add gnutls hash provider crypto: add gnutls cipher provider crypto: introduce build system for gnutls crypto backend crypto: flip priority of backends to prefer gcrypt crypto: replace 'des-rfb' cipher with 'des' crypto: delete built-in XTS cipher mode support crypto: delete built-in DES implementation crypto: add crypto tests for single block DES-ECB and DES-CBC crypto: drop custom XTS support in gcrypt driver ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
438951e8 |
| 15-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-plugins-140721-5' into staging Testing and plugin updates: - custom runner playbooks for configuring GitLab run
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-plugins-140721-5' into staging Testing and plugin updates: - custom runner playbooks for configuring GitLab runners - integrate Cirrus jobs into GitLab via cirrus-run - clean-up docker package lists - bump NetBSD to 9.2 - bump OpenBSD to 6.9 - make test-mmap more hexagon friendly - fixup handling of hostaddr for plugins - disallow some incompatible plugin configurations - fix handling of -ldl for BSDs - remove some old unused symbols from the plugin symbol map - enable plugins by default for most TCG builds - honour main build -Wall settings for plugins - new execlog plugin - new cache modelling plugin - fix io_uring build regression - disable modular TCG on Darwin # gpg: Signature made Wed 14 Jul 2021 15:56:27 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-and-plugins-140721-5: (44 commits) MAINTAINERS: Added myself as a reviewer for TCG Plugins docs/devel: Added cache plugin to the plugins docs plugins/cache: Added FIFO and LRU eviction policies plugins/cache: Enable cache parameterization plugins: Added a new cache modelling plugin docs/devel: tcg-plugins: add execlog plugin description contrib/plugins: add execlog to log instruction execution and memory access contrib/plugins: enable -Wall for building plugins tcg/plugins: enable by default for most TCG builds configure: stop user enabling plugins on Windows for now configure: add an explicit static and plugins check configure: don't allow plugins to be enabled for a non-TCG build tcg/plugins: remove some stale entries from the symbol list meson.build: relax the libdl test to one for the function dlopen meson.build: move TCG plugin summary output plugins: fix-up handling of internal hostaddr for 32 bit tests/tcg: make test-mmap a little less aggressive tests/vm: update openbsd to release 6.9 tests/vm: update NetBSD to 9.2 tests/docker: expand opensuse-leap package list ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
a9649a71 |
| 14-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/cleber-gitlab/tags/python-next-pull-request' into staging Python and Acceptance Tests - New SMMUv3 and Intel IOMMU tests - Respect "cpu" ta
Merge remote-tracking branch 'remotes/cleber-gitlab/tags/python-next-pull-request' into staging Python and Acceptance Tests - New SMMUv3 and Intel IOMMU tests - Respect "cpu" tags and reduce boiler plate code - Improved logging of qemu execution output - Other misc improvements # gpg: Signature made Tue 13 Jul 2021 22:11:36 BST # gpg: using RSA key 7ABB96EB8B46B94D5E0FE9BB657E8D33A5F209F3 # gpg: Good signature from "Cleber Rosa <crosa@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 7ABB 96EB 8B46 B94D 5E0F E9BB 657E 8D33 A5F2 09F3 * remotes/cleber-gitlab/tags/python-next-pull-request: (23 commits) tests/acceptance/cpu_queries.py: use the proper logging channels tests/acceptance/linux_ssh_mips_malta.py: drop identical setUp Acceptance tests: do not try to reuse packages from the system python: Configure tox to skip missing interpreters tests/acceptance: Handle cpu tag on x86_cpu_model_versions tests tests/acceptance: Add set_vm_arg() to the Test class python/qemu: Add args property to the QEMUMachine class tests/acceptance: Tagging tests with "cpu:VALUE" tests/acceptance: Let the framework handle "cpu:VALUE" tagged tests tests/acceptance: Fix mismatch on cpu tagged tests tests/acceptance: Automatic set -cpu to the test vm tests/acceptance: Tag NetBSD tests as 'os:netbsd' avocado_qemu: Add Intel iommu tests avocado_qemu: Add SMMUv3 tests Acceptance Tests: Add default kernel params and pxeboot url to the KNOWN_DISTROS collection avocado_qemu: Fix KNOWN_DISTROS map into the LinuxDistro class tests/acceptance: Ignore binary data sent on serial console Acceptance Tests: support choosing specific distro and version Acceptance Tests: move definition of distro checksums to the framework Acceptance Tests: rename attribute holding the distro image checksum ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
1f966c7c |
| 14-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/mdroth/tags/qga-pull-2021-07-13-tag' into staging qemu-ga patch queue for soft-freeze * add support for Windows Server 2022 in get-osinfo comma
Merge remote-tracking branch 'remotes/mdroth/tags/qga-pull-2021-07-13-tag' into staging qemu-ga patch queue for soft-freeze * add support for Windows Server 2022 in get-osinfo command # gpg: Signature made Tue 13 Jul 2021 19:10:05 BST # gpg: using RSA key CEACC9E15534EBABB82D3FA03353C9CEF108B584 # gpg: Good signature from "Michael Roth <flukshun@gmail.com>" [full] # gpg: aka "Michael Roth <mdroth@utexas.edu>" [full] # gpg: aka "Michael Roth <mdroth@linux.vnet.ibm.com>" [full] # Primary key fingerprint: CEAC C9E1 5534 EBAB B82D 3FA0 3353 C9CE F108 B584 * remotes/mdroth/tags/qga-pull-2021-07-13-tag: qga-win: Add support of Windows Server 2022 in get-osinfo command Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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20a96761 |
| 14-Jul-2021 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-misc-20210713' into staging Cleanup alpha, hppa, or1k wrt tcg_constant_tl. Implement x86 fcs:fip, fds:fdp. Trivial x86 watc
Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-misc-20210713' into staging Cleanup alpha, hppa, or1k wrt tcg_constant_tl. Implement x86 fcs:fip, fds:fdp. Trivial x86 watchpoint cleanup. # gpg: Signature made Tue 13 Jul 2021 17:36:29 BST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-misc-20210713: target/hppa: Clean up DisasCond target/hppa: Use tcg_constant_* target/openrisc: Use dc->zero in gen_add, gen_addc target/openrisc: Cache constant 0 in DisasContext target/openrisc: Use tcg_constant_tl for dc->R0 target/openrisc: Use tcg_constant_* target/alpha: Use tcg_constant_* elsewhere target/alpha: Use tcg_constant_i64 for zero and lit target/alpha: Use dest_sink for HW_RET temporary target/alpha: Store set into rx flag target/i386: Correct implementation for FCS, FIP, FDS and FDP target/i386: Split out do_fninit target/i386: Trivial code motion and code style fix target/i386: Tidy hw_breakpoint_remove Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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6e94937a |
| 08-Jul-2021 |
Richard Henderson <richard.henderson@linaro.org> |
target/hppa: Clean up DisasCond The a0_is_n flag is redundant with comparing a0 to cpu_psw_n. The a1_is_0 flag can be removed by initializing a1 to $0, which also means that cond_pre
target/hppa: Clean up DisasCond The a0_is_n flag is redundant with comparing a0 to cpu_psw_n. The a1_is_0 flag can be removed by initializing a1 to $0, which also means that cond_prep can be removed entirely. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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