target/hppa: Implement CLRBTS, POPBTS, PUSHBTS, PUSHNOM

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement SHRPD

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement EXTRD

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement DEPD, DEPDI

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Implement LDD, LDCD, LDDA, STD, STDA

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode ADDB double-word

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode CMPIB double-word

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode d for cmpb instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode d for bb instructions

Manipulate the shift count so that the bit to be tested
is always placed at the MSB.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode d for sub instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode d for add instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode d for cmpclr instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode d for unit instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Decode d for logical instructions

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Remove TARGET_HPPA64

Allow both user-only and system mode to run pa2.0 cpus.
Avoid creating a separate qemu-system-hppa64 binary;
force the qemu-hppa binary to use TARGET_ABI32.

Signed

target/hppa: Remove TARGET_HPPA64

Allow both user-only and system mode to run pa2.0 cpus.
Avoid creating a separate qemu-system-hppa64 binary;
force the qemu-hppa binary to use TARGET_ABI32.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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target/hppa: Pass d to do_unit_cond

Hoist the resolution of d up one level above do_unit_cond.
All computations are logical, and are simplified by using a mask of the
correct width, after which the

target/hppa: Pass d to do_unit_cond

Hoist the resolution of d up one level above do_unit_cond.
All computations are logical, and are simplified by using a mask of the
correct width, after which the result may be compared with zero.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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target/hppa: Pass d to do_sed_cond

Hoist the resolution of d up one level above do_sed_cond.
The MOVB comparison and the existing shift/extract/deposit
are all 32-bit.

Signed-off-by: Richard Hender

target/hppa: Pass d to do_sed_cond

Hoist the resolution of d up one level above do_sed_cond.
The MOVB comparison and the existing shift/extract/deposit
are all 32-bit.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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target/hppa: Pass d to do_log_cond

Hoist the resolution of d up one level above do_log_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Pass d to do_sub_cond

Hoist the resolution of d up one level above do_sub_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Pass d to do_cond

Hoist the resolution of d up one level above do_cond.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: sar register allows only 5 bits on 32-bit CPU

The sar shift amount register is limited to 5 bits when running
a 32-bit CPU. Strip off the remaining bits.

The interesting part is, that

target/hppa: sar register allows only 5 bits on 32-bit CPU

The sar shift amount register is limited to 5 bits when running
a 32-bit CPU. Strip off the remaining bits.

The interesting part is, that this register allows to detect at runtime
if a physical CPU is capable to execute PA2.0 (64-bit) instructions.

Signed-off-by: Helge Deller <deller@gmx.de>

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target/hppa: Mask inputs in copy_iaoq_entry

Ensure that the destination is always a valid GVA offset.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

target/hppa: Use copy_iaoq_entry for link in do_ibranch

We need to make sure the link is masked properly along the
use_nullify_skip path. The other three settings of a link
register already use thi

target/hppa: Use copy_iaoq_entry for link in do_ibranch

We need to make sure the link is masked properly along the
use_nullify_skip path. The other three settings of a link
register already use this.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb]

This will be how we ensure that the IAOQ is always
valid per PSW.W, therefore all stores to these two
variables must be done with this fu

target/hppa: Always use copy_iaoq_entry to set cpu_iaoq_[fb]

This will be how we ensure that the IAOQ is always
valid per PSW.W, therefore all stores to these two
variables must be done with this function.

Use third argument -1 if the destination is always dynamic,
and fourth argument NULL if the destination is always static.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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target/hppa: Pass DisasContext to copy_iaoq_entry

Interface change only, no functional effect.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>