95c9e220 | 13-Nov-2024 |
Richard Henderson <richard.henderson@linaro.org> |
linux-user/arm: Select vdso for be8 and be32 modes
In be8 mode, instructions are little-endian. In be32 mode, instructions are big-endian.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/23
linux-user/arm: Select vdso for be8 and be32 modes
In be8 mode, instructions are little-endian. In be32 mode, instructions are big-endian.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2333 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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4ae7d11b | 27-Sep-2024 |
Peter Maydell <peter.maydell@linaro.org> |
Merge tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu into staging
target/ppc: Fix lxvx/stxvx facility check linux-user: update syscall_nr.h to Linux v6.10 linux-user: update syscall.tbl
Merge tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu into staging
target/ppc: Fix lxvx/stxvx facility check linux-user: update syscall_nr.h to Linux v6.10 linux-user: update syscall.tbl to Linux v6.11 tcg: Fix iteration step in 32-bit gvec operation tcg: Propagate new TCGOp to add_as_label_use tcg/*: Do not expand cmp_vec, cmpsel_vec early tcg/optimize: Fold movcond with true and false values identical tcg/optimize: Optimize cmp_vec and cmpsel_vec tcg/optimize: Optimize bitsel_vec tcg/i386: Optimize cmpsel with constant 0 operand 3. tcg/i386: Implement cmp_vec with avx512 insns tcg/i386: Implement cmpsel_vec with avx512 insns tcg/i386: Implement vector TST{EQ,NE} for avx512 tcg/ppc: Implement cmpsel_vec and optimize with constant 0/-1 arguments tcg/s390x: Implement cmpsel_vec and optimize with constant 0/-1 arguments
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* tag 'pull-tcg-20240922' of https://gitlab.com/rth7680/qemu: (31 commits) linux-user: update syscall.tbl to Linux v6.11 linux-user,loongarch: move to syscalltbl file linux-user,hexagon: move to syscalltbl file linux-user,riscv: move to syscalltbl file linux-user,openrisc: move to syscalltbl file linux-user,aarch64: move to syscalltbl file linux-user: update syscall.tbl to Linux v6.10 linux-user, mips: update syscall-args-o32.c.inc to Linux v6.10 linux-user: update syscall_nr.h to Linux v6.10 target/ppc: Fix lxvx/stxvx facility check tcg/s390x: Optimize cmpsel with constant 0/-1 arguments tcg/s390x: Implement cmpsel_vec tcg/ppc: Optimize cmpsel with constant 0/-1 arguments tcg/ppc: Implement cmpsel_vec tcg/i386: Implement vector TST{EQ,NE} for avx512 tcg/i386: Implement cmpsel_vec with avx512 insns tcg/i386: Add predicate parameters to tcg_out_evex_opc tcg/i386: Implement cmp_vec with avx512 insns tcg/i386: Optimize cmpsel with constant 0 operand 3. tcg/optimize: Optimize bitsel_vec ...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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a55b9e72 | 03-Aug-2023 |
Helge Deller <deller@gmx.de> |
linux-user: Emulate /proc/cpuinfo on aarch64 and arm
Add emulation for /proc/cpuinfo for arm architecture. The output below mimics output as seen on debian porterboxes.
aarch64 output example:
pro
linux-user: Emulate /proc/cpuinfo on aarch64 and arm
Add emulation for /proc/cpuinfo for arm architecture. The output below mimics output as seen on debian porterboxes.
aarch64 output example:
processor : 0 model name : ARMv8 Processor rev 0 (v8l) BogoMIPS : 100.00 Features : swp half thumb fast_mult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae aes pmull sha1 sha2 crc32 CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x1 CPU part : 0xd07 CPU revision : 0
arm 32-bit output example:
processor : 0 model name : ARMv7 Processor rev 5 (armv7l) BogoMIPS : 100.00 Features : swp half thumb fast_mult vfp edsp thumbee neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x0f CPU part : 0xc07 CPU revision : 5
Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20230803214450.647040-3-deller@gmx.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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