| d704a13d | 07-Oct-2025 |
Stefan Hajnoczi <stefanha@redhat.com> |
block: use pwrite_zeroes_alignment when writing first sector
Since commit 5634622bcb33 ("file-posix: allow BLKZEROOUT with -t writeback"), qemu-img create errors out on a Linux loop block device wit
block: use pwrite_zeroes_alignment when writing first sector
Since commit 5634622bcb33 ("file-posix: allow BLKZEROOUT with -t writeback"), qemu-img create errors out on a Linux loop block device with a 4 KB sector size:
# dd if=/dev/zero of=blockfile bs=1M count=1024 # losetup --sector-size 4096 /dev/loop0 blockfile # qemu-img create -f raw /dev/loop0 1G Formatting '/dev/loop0', fmt=raw size=1073741824 qemu-img: /dev/loop0: Failed to clear the new image's first sector: Invalid argument
Use the pwrite_zeroes_alignment block limit to avoid misaligned fallocate(2) or ioctl(BLKZEROOUT) in the block/file-posix.c block driver.
Cc: qemu-stable@nongnu.org Fixes: 5634622bcb33 ("file-posix: allow BLKZEROOUT with -t writeback") Reported-by: Jean-Louis Dupond <jean-louis@dupond.be> Buglink: https://gitlab.com/qemu-project/qemu/-/issues/3127 Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-ID: <20251007141700.71891-3-stefanha@redhat.com> Tested-by: Fiona Ebner <f.ebner@proxmox.com> Reviewed-by: Fiona Ebner <f.ebner@proxmox.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
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| 593fe98d | 29-Oct-2025 |
Gerd Hoffmann <kraxel@redhat.com> |
igvm: add support for initial register state load in native mode
Add IgvmNativeVpContextX64 struct holding the register state (see igvm spec), and the qigvm_x86_load_context() function to load the r
igvm: add support for initial register state load in native mode
Add IgvmNativeVpContextX64 struct holding the register state (see igvm spec), and the qigvm_x86_load_context() function to load the register state.
Wire up using two new functions: qigvm_x86_set_vp_context() is called from igvm file handling code and stores the boot processor context. qigvm_x86_bsp_reset() is called from i386 target cpu reset code and loads the context into the cpu registers.
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Luigi Leonardi <leonardi@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-ID: <20251029105555.2492276-5-kraxel@redhat.com>
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| 13abf2fc | 29-Oct-2025 |
Gerd Hoffmann <kraxel@redhat.com> |
igvm: add support for igvm memory map parameter in native mode
Add and wire up qigvm_x86_get_mem_map_entry function which converts the e820 table into an igvm memory map parameter. This makes igvm
igvm: add support for igvm memory map parameter in native mode
Add and wire up qigvm_x86_get_mem_map_entry function which converts the e820 table into an igvm memory map parameter. This makes igvm files for the native (non-confidential) platform with memory map parameter work.
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Luigi Leonardi <leonardi@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-ID: <20251029105555.2492276-4-kraxel@redhat.com>
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| 451e7b7a | 29-Oct-2025 |
Gerd Hoffmann <kraxel@redhat.com> |
igvm: move igvm.h file to include/system
Prepare for arch-specific igvm code being added to the code base.
Reviewed-by: Ani Sinha <anisinha@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@red
igvm: move igvm.h file to include/system
Prepare for arch-specific igvm code being added to the code base.
Reviewed-by: Ani Sinha <anisinha@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Reviewed-by: Luigi Leonardi <leonardi@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-ID: <20251029105555.2492276-2-kraxel@redhat.com>
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| 53b41bb7 | 01-Nov-2025 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'pull-target-arm-20251031' of https://gitlab.com/pm215/qemu into staging
target-arm queue: * hw/gpio/pl061: Declare pullups/pulldowns as 8-bit types * docs/system/arm/virt: Document use
Merge tag 'pull-target-arm-20251031' of https://gitlab.com/pm215/qemu into staging
target-arm queue: * hw/gpio/pl061: Declare pullups/pulldowns as 8-bit types * docs/system/arm/virt: Document user-creatable SMMUv3 * docs/system/security: Restrict "virtualization use case" to specific machines * target/arm: Add assert to arm_to_core_mmu_idx() * hw/arm/virt: remove deprecated virt-4.1 and virt-4.2 machine types * hvf: Refactorings and cleanups
# -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmkFAKcZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3oSZD/0ekFlrMRFZCYg7ie9t/Cgz # 7OBZGjK+WfuKsD9odYesZzxJ+aPMBQHu6l/44cYaqf+NTRM2hI9ZeaV9e4fXPG0e # fYImjYMLKPHj4UTam42uN0btl3poq+oaVPKqDPovy+9E09NctO4fmTl7Zys6pH/1 # EwznCk1x3+JLW0xPXXEvfTniB1nB+hvKA/n7NS0qe6n2ddenhQzG8DpdnGEGB+75 # whMwhE/UJ5Y8rP6/Nfc8XqzgU6fmEpPsDRHjDCULy/CiGCV6k8/C8J94UTf2SExh # iiMLySUb2Rv6qIL2nJX2+xup79UB7umxxoIL0eeN1U/M1L7zMB64rlcU/cym2I40 # mAFuW2qzdsADnpRP8d4KTMJQmFxtZuKuxpkapvIFuusiKq5vBwTxfzyLWdM6nPI9 # 7tbKImzLxC1mnOAT0QeZYhLrWMZgQi3tBcS852JAXpiW1eT7SWsl59bKNgCVzI7r # malptTniE1G+F4VWlghApLympBhNMMaFBfY4XBQ+VxEu+JNhO+MQlJhcLVbqX+oY # m2OQhPHRv2YUM2VGv40JuzaUE1cXHXNsC7s9hHsB/3UwIp3fXOsdGuq6KviHdcbP # moQn3M8S/vdFB+1spkhVxS7xgIZJo9f2kaTe9VlpEY7/k5n36BTsxPN6Uae2gIVq # w4qzOjXFEyeIxLLKQZqyZg== # =9IV+ # -----END PGP SIGNATURE----- # gpg: Signature made Fri 31 Oct 2025 07:32:07 PM CET # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [unknown] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [unknown] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [unknown] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20251031' of https://gitlab.com/pm215/qemu: (38 commits) accel/hvf: Trace prefetch abort target/arm/hvf/hvf: Document $pc adjustment in HVF & SMC target/arm: Share ARM_PSCI_CALL trace event between TCG and HVF target/arm: Re-use arm_is_psci_call() in HVF target/arm/hvf: Rename 'vgic' -> 'emu_reginfo' in trace events target/arm: Rename init_cpreg_list() -> arm_init_cpreg_list() accel/hvf: Restrict ARM specific fields of AccelCPUState target/arm: Call aarch64_add_pauth_properties() once in host_initfn() accel/hvf: Guard hv_vcpu_run() between cpu_exec_start/end() calls cpus: Trace cpu_exec_start() and cpu_exec_end() calls target/arm/hvf: Keep calling hv_vcpu_run() in loop target/arm/hvf: Factor hvf_handle_vmexit() out target/i386/hvf: Factor hvf_handle_vmexit() out target/arm/hvf: Factor hvf_handle_exception() out target/arm/hvf: switch hvf_arm_get_host_cpu_features to not create a vCPU target/arm/hvf: Simplify hvf_arm_get_host_cpu_features() target/arm/hvf: Hardcode Apple MIDR accel/hvf: Implement hvf_arch_vcpu_destroy() target/arm/hvf: Mention hvf_inject_interrupts() must run on vCPU thread accel/hvf: Mention hvf_arch_update_guest_debug() must run on vCPU ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| c5d60e59 | 01-Nov-2025 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'audio-test-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging
Audio clean-ups
# -----BEGIN PGP SIGNATURE----- # # iQJQBAABCgA6FiEEh6m9kz+HxgbSdvYt2ujhCXWWnOUFAmkEWqwc
Merge tag 'audio-test-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging
Audio clean-ups
# -----BEGIN PGP SIGNATURE----- # # iQJQBAABCgA6FiEEh6m9kz+HxgbSdvYt2ujhCXWWnOUFAmkEWqwcHG1hcmNhbmRy # ZS5sdXJlYXVAcmVkaGF0LmNvbQAKCRDa6OEJdZac5a4RD/49KcP8h/5+QT3nu703 # OL/c/+M0DEZCVikzbj1T+nZNlUZtto/wE1vY0/xxzoyMh/4XbUFI0b/YK8WcQyUx # ozrWOCi6TquS1QpR62FBmDJ6QDA2KteTF8Zq/owdFj+l7VJ5F5mzcuuFCxLx1EVH # 7qOIf37Vk4r8jz42CLRTusPGQZLSvS8LbTBP62guauXlVAKVWI8k9macRSqoTBRo # VrQO3QC/JFSqkB2jGfes8AMU+RWLYPG3ICCf0UYHH/kMik/JEL+1arx7au7oukTb # 3kp8cxGnuJzBKCvY8SLwQF3YiCotYQIjSkvAQrMYBXalPBjQIIh+vzegcF1D+xZb # 6KR4kh3oXPHtVCG2AXcxA4IuAi50jYFPn6TgDkRrUAEhsOqOxLo5bmZsqWK7L3/u # 61jLKSjLRSc+NjhwHN0YVy1ocdsLf2z1LQNHjC1TuxrgI//9fQnOE2gASb8tmJGg # BlPYp5h6G50IEaACzlZEtudWpKRb/XyflWpHbWte0VUO9dpz/cUvO1P38CpPD1dr # ohENb8eLn0L23M12tUABV0IoA729phBYh3Eua9uIzEVfuRVfoPCuocx6VxQked91 # SZr7X9G80Nyh5YYiMlrwpN8eDgPtKfW5JwI2wYME6clGLnf/catkqCl/qp4nQeG5 # LPZiFy5Krz+QuSq41DjcSWRD+g== # =qTgA # -----END PGP SIGNATURE----- # gpg: Signature made Fri 31 Oct 2025 07:43:56 AM CET # gpg: using RSA key 87A9BD933F87C606D276F62DDAE8E10975969CE5 # gpg: issuer "marcandre.lureau@redhat.com" # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" [unknown] # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" [unknown] # gpg: WARNING: The key's User ID is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5
* tag 'audio-test-pull-request' of https://gitlab.com/marcandre.lureau/qemu: (36 commits) audio: deprecate HMP audio commands audio: Rename @endianness argument as @big_endian for clarity audio: Remove pointless local variables audio: drop needless audio_driver "descr" field audio: move capture API to own header audio: cleanup, use bool for booleans audio: remove dependency on spice header audio: move audio.h under include/qemu/ audio/dbus: use a helper function to set the backend dbus server audio: remove QEMUSoundCard audio: rename AudioState -> AudioBackend audio: move internal APIs to audio_int.h audio/replay: fix type punning audio: introduce AUD_set_volume_{in,out}_lr() audio: remove AUDIO_HOST_ENDIANNESS audio: remove some needless headers audio: initialize card_head during object init audio: register and unregister vmstate with AudioState audio: keep vmstate handle with AudioState audio: drop needless error message ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| 2ad75638 | 28-Oct-2025 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
accel/hvf: Restrict ARM specific fields of AccelCPUState
Do not expose ARM specific fields to X86 implementation, allowing to use the proper 'hv_vcpu_exit_t' type.
Signed-off-by: Philippe Mathieu-D
accel/hvf: Restrict ARM specific fields of AccelCPUState
Do not expose ARM specific fields to X86 implementation, allowing to use the proper 'hv_vcpu_exit_t' type.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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| feee55d3 | 28-Oct-2025 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
accel/hvf: Implement hvf_arch_vcpu_destroy()
Call hv_vcpu_destroy() to destroy our vCPU context.
As hv_vcpu_destroy() must be called by the owning thread, document hvf_arch_vcpu_destroy() also does
accel/hvf: Implement hvf_arch_vcpu_destroy()
Call hv_vcpu_destroy() to destroy our vCPU context.
As hv_vcpu_destroy() must be called by the owning thread, document hvf_arch_vcpu_destroy() also does.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Mads Ynddal <mads@ynddal.dk> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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| 073e7e1c | 28-Oct-2025 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
accel/hvf: Mention hvf_arch_update_guest_debug() must run on vCPU
Since hvf_arch_update_guest_debug() calls hvf_arch_set_traps() and hvf_arch_update_guest_debug(), which must run on a vCPU, it also
accel/hvf: Mention hvf_arch_update_guest_debug() must run on vCPU
Since hvf_arch_update_guest_debug() calls hvf_arch_set_traps() and hvf_arch_update_guest_debug(), which must run on a vCPU, it also must. Mention it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Mads Ynddal <mads@ynddal.dk> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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| a6413843 | 28-Oct-2025 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
accel/hvf: Mention hvf_arch_init_vcpu() must run on vCPU thread
hvf_arch_init_vcpu(), along with hvf_put_guest_debug_registers() and hvf_put_gdbstub_debug_registers(), calls hv_vcpu_set_sys_reg(), w
accel/hvf: Mention hvf_arch_init_vcpu() must run on vCPU thread
hvf_arch_init_vcpu(), along with hvf_put_guest_debug_registers() and hvf_put_gdbstub_debug_registers(), calls hv_vcpu_set_sys_reg(), which must run on a vCPU. Mention they also must.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Mads Ynddal <mads@ynddal.dk> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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| 1182ede1 | 28-Oct-2025 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
accel/hvf: Rename hvf_put|get_registers -> hvf_arch_put|get_registers
hvf_put_registers() and hvf_get_registers() are implemented per target, rename them using the 'hvf_arch_' prefix following the p
accel/hvf: Rename hvf_put|get_registers -> hvf_arch_put|get_registers
hvf_put_registers() and hvf_get_registers() are implemented per target, rename them using the 'hvf_arch_' prefix following the per target pattern.
Since they call hv_vcpu_set_reg() / hv_vcpu_get_reg(), mention they must be called on the vCPU.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Mads Ynddal <mads@ynddal.dk> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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| 963f1576 | 28-Oct-2025 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
accel/hvf: Rename hvf_vcpu_exec() -> hvf_arch_vcpu_exec()
hvf_vcpu_exec() is implemented per target, rename it as hvf_arch_vcpu_exec(), following the per target pattern.
Since it calls hv_vcpu_run(
accel/hvf: Rename hvf_vcpu_exec() -> hvf_arch_vcpu_exec()
hvf_vcpu_exec() is implemented per target, rename it as hvf_arch_vcpu_exec(), following the per target pattern.
Since it calls hv_vcpu_run(), mention it must be called on the vCPU.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Mads Ynddal <mads@ynddal.dk> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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| 1e4ebc89 | 14-Oct-2025 |
Marc-André Lureau <marcandre.lureau@redhat.com> |
audio: move audio.h under include/qemu/
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp> |
| 04536d70 | 14-Oct-2025 |
Marc-André Lureau <marcandre.lureau@redhat.com> |
audio/replay: fix type punning
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
| 3d8412c2 | 03-Oct-2025 |
Wilfred Mallawa <wilfred.mallawa@wdc.com> |
spdm: define SPDM transport enum types
SPDM maybe used over different transports. This patch specifies the trasnport types as an enum with a qdev property definition such that a user input transport
spdm: define SPDM transport enum types
SPDM maybe used over different transports. This patch specifies the trasnport types as an enum with a qdev property definition such that a user input transport type (string) can be mapped directly into the respective SPDM transportenum for internal use.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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| e5534abe | 03-Oct-2025 |
Wilfred Mallawa <wilfred.mallawa@wdc.com> |
hw/nvme: add NVMe Admin Security SPDM support
Adds the NVMe Admin Security Send/Receive command support with support for DMTFs SPDM. The transport binding for SPDM is defined in the DMTF DSP0286.
S
hw/nvme: add NVMe Admin Security SPDM support
Adds the NVMe Admin Security Send/Receive command support with support for DMTFs SPDM. The transport binding for SPDM is defined in the DMTF DSP0286.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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| 64a9336a | 03-Oct-2025 |
Wilfred Mallawa <wilfred.mallawa@wdc.com> |
spdm: add spdm storage transport virtual header
This header contains the transport encoding for an SPDM message that uses the SPDM over Storage transport as defined by the DMTF DSP0286.
Note that i
spdm: add spdm storage transport virtual header
This header contains the transport encoding for an SPDM message that uses the SPDM over Storage transport as defined by the DMTF DSP0286.
Note that in the StorageSpdmTransportHeader structure, security_protocol field is defined in the SCSI Primary Commands 5 (SPC-5) specification. The NVMe specification also refers to the SPC-5 for this definition. The security_protocol_specific field is defined in DSP0286 and is referred to as SP Specific for NVMe and ATA.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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| 169e8d0c | 03-Oct-2025 |
Wilfred Mallawa <wilfred.mallawa@wdc.com> |
spdm-socket: add seperate send/recv functions
This is to support uni-directional transports such as SPDM over Storage. As specified by the DMTF DSP0286.
Also update spdm_socket_rsp() to use the new
spdm-socket: add seperate send/recv functions
This is to support uni-directional transports such as SPDM over Storage. As specified by the DMTF DSP0286.
Also update spdm_socket_rsp() to use the new send()/receive() functions. For the case of spdm_socket_receive(), this allows us to do error checking in one place with the addition of spdm_socket_command_valid().
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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| 1b21518f | 22-Oct-2025 |
Marc-André Lureau <marcandre.lureau@redhat.com> |
char: rename CharBackend->CharFrontend
The actual backend is "Chardev", CharBackend is the frontend side of it (whatever talks to the backend), let's rename it for readability.
Signed-off-by: Marc-
char: rename CharBackend->CharFrontend
The actual backend is "Chardev", CharBackend is the frontend side of it (whatever talks to the backend), let's rename it for readability.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Link: https://lore.kernel.org/r/20251022074612.1258413-1-marcandre.lureau@redhat.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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| 665a8035 | 07-Oct-2025 |
Philippe Mathieu-Daudé <philmd@linaro.org> |
accel/kvm: Introduce KvmPutState enum
Join the 3 KVM_PUT_*_STATE definitions in a single enum.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Harsh Prateek Bora <harshpb@lin
accel/kvm: Introduce KvmPutState enum
Join the 3 KVM_PUT_*_STATE definitions in a single enum.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/r/20251008040715.81513-3-philmd@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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| 1188b07e | 09-Oct-2025 |
Richard Henderson <richard.henderson@linaro.org> |
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* i386: fix migration issues in 10.1 * target/i386/mshv: new accelerator * rust: use glib-sys-rs * rust: fixes for docker tes
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* i386: fix migration issues in 10.1 * target/i386/mshv: new accelerator * rust: use glib-sys-rs * rust: fixes for docker tests
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* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (35 commits) rust: fix path to rust_root_crate.sh tests/docker: make --enable-rust overridable with EXTRA_CONFIGURE_OPTS MAINTAINERS: Add maintainers for mshv accelerator docs: Add mshv to documentation target/i386/mshv: Use preallocated page for hvcall qapi/accel: Allow to query mshv capabilities accel/mshv: Handle overlapping mem mappings target/i386/mshv: Implement mshv_vcpu_run() target/i386/mshv: Write MSRs to the hypervisor target/i386/mshv: Integrate x86 instruction decoder/emulator target/i386/mshv: Register MSRs with MSHV target/i386/mshv: Register CPUID entries with MSHV target/i386/mshv: Set local interrupt controller state target/i386/mshv: Implement mshv_arch_put_registers() target/i386/mshv: Implement mshv_get_special_regs() target/i386/mshv: Implement mshv_get_standard_regs() target/i386/mshv: Implement mshv_store_regs() target/i386/mshv: Add CPU create and remove logic accel/mshv: Add vCPU signal handling accel/mshv: Add vCPU creation and execution loop ...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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| e4a20afc | 02-Oct-2025 |
Magnus Kulke <magnuskulke@linux.microsoft.com> |
target/i386/mshv: Use preallocated page for hvcall
There are hvcalls that are invoked during MMIO exits, the payload is of dynamic size. To avoid heap allocations we can use preallocated pages as in
target/i386/mshv: Use preallocated page for hvcall
There are hvcalls that are invoked during MMIO exits, the payload is of dynamic size. To avoid heap allocations we can use preallocated pages as in/out buffer for those calls. A page is reserved per vCPU and used for set/get register hv calls.
Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20250916164847.77883-26-magnuskulke@linux.microsoft.com [Use standard MAX_CONST macro; mshv.h/mshv_int.h split. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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| e7b08dfb | 16-Sep-2025 |
Praveen K Paladugu <prapal@microsoft.com> |
qapi/accel: Allow to query mshv capabilities
Allow to query mshv capabilities via query-mshv QMP and info mshv HMP commands.
Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Acked-by:
qapi/accel: Allow to query mshv capabilities
Allow to query mshv capabilities via query-mshv QMP and info mshv HMP commands.
Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Acked-by: Dr. David Alan Gilbert <dave@treblig.org> Link: https://lore.kernel.org/r/20250916164847.77883-25-magnuskulke@linux.microsoft.com [Fix "since" version. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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| efc40933 | 16-Sep-2025 |
Magnus Kulke <magnuskulke@linux.microsoft.com> |
accel/mshv: Handle overlapping mem mappings
QEMU maps certain regions into the guest multiple times, as seen in the trace below. Currently the MSHV kernel driver will reject those mappings. To worka
accel/mshv: Handle overlapping mem mappings
QEMU maps certain regions into the guest multiple times, as seen in the trace below. Currently the MSHV kernel driver will reject those mappings. To workaround this, a record is kept (a static global list of "slots", inspired by what the HVF accelerator has implemented). An overlapping region is not registered at the hypervisor, and marked as mapped=false. If there is an UNMAPPED_GPA exit, we can look for a slot that is unmapped and would cover the GPA. In this case we map out the conflicting slot and map in the requested region.
mshv_set_phys_mem add=1 name=pc.bios mshv_map_memory => u_a=7ffff4e00000 gpa=00fffc0000 size=00040000 mshv_set_phys_mem add=1 name=ioapic mshv_set_phys_mem add=1 name=hpet mshv_set_phys_mem add=0 name=pc.ram mshv_unmap_memory u_a=7fff67e00000 gpa=0000000000 size=80000000 mshv_set_phys_mem add=1 name=pc.ram mshv_map_memory u_a=7fff67e00000 gpa=0000000000 size=000c0000 mshv_set_phys_mem add=1 name=pc.rom mshv_map_memory u_a=7ffff4c00000 gpa=00000c0000 size=00020000 mshv_set_phys_mem add=1 name=pc.bios mshv_remap_attempt => u_a=7ffff4e20000 gpa=00000e0000 size=00020000
The mapping table is guarded by a mutex for concurrent modification and RCU mechanisms for concurrent reads. Writes occur rarely, but we'll have to verify whether an unmapped region exist for each UNMAPPED_GPA exit, which happens frequently.
Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20250916164847.77883-24-magnuskulke@linux.microsoft.com [Fix format strings for trace-events; mshv.h/mshv_int.h split. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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| 9bc6a1d2 | 16-Sep-2025 |
Magnus Kulke <magnuskulke@linux.microsoft.com> |
target/i386/mshv: Integrate x86 instruction decoder/emulator
Connect the x86 instruction decoder and emulator to the MSHV backend to handle intercepted instructions. This enables software emulation
target/i386/mshv: Integrate x86 instruction decoder/emulator
Connect the x86 instruction decoder and emulator to the MSHV backend to handle intercepted instructions. This enables software emulation of MMIO operations in MSHV guests. MSHV has a translate_gva hypercall that is used to accessing the physical guest memory.
A guest might read from unmapped memory regions (e.g. OVMF will probe 0xfed40000 for a vTPM). In those cases 0xFF bytes is returned instead of aborting the execution.
Signed-off-by: Magnus Kulke <magnuskulke@linux.microsoft.com> Link: https://lore.kernel.org/r/20250916164847.77883-21-magnuskulke@linux.microsoft.com [mshv.h/mshv_int.h split. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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