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24bd283b |
| 16-Apr-2024 |
Nicholas Piggin <npiggin@gmail.com> |
ppc/pnv: Implement ADU access to LPC space
One of the functions of the ADU is indirect memory access engines that send and receive data via ADU registers.
This implements the ADU LPC memory access
ppc/pnv: Implement ADU access to LPC space
One of the functions of the ADU is indirect memory access engines that send and receive data via ADU registers.
This implements the ADU LPC memory access functionality sufficiently for IBM proprietary firmware to access the UART and print characters to the serial port as it does on real hardware.
This requires a linkage between adu and lpc, which allows adu to perform memory access in the lpc space.
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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53f18b3e |
| 23-Feb-2024 |
Nicholas Piggin <npiggin@gmail.com> |
ppc/pnv: Begin a more complete ADU LPC model for POWER9/10
This implements a framework for an ADU unit model.
The ADU unit actually implements XSCOM, which is the bridge between MMIO and PIB. Howev
ppc/pnv: Begin a more complete ADU LPC model for POWER9/10
This implements a framework for an ADU unit model.
The ADU unit actually implements XSCOM, which is the bridge between MMIO and PIB. However it also includes control and status registers and other functions that are exposed as PIB (xscom) registers.
To keep things simple, pnv_xscom.c remains the XSCOM bridge implementation, and pnv_adu.c implements the ADU registers and other functions.
So far, just the ADU no-op registers in the pnv_xscom.c default handler are moved over to the adu model.
Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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