Revision tags: v3.1.0, v3.1.0-rc5, v3.1.0-rc4, v3.1.0-rc3, v3.1.0-rc2, v3.1.0-rc1, v3.1.0-rc0, libfdt-20181002, ppc-for-3.1-20180925, ppc-for-3.1-20180907, ppc-for-3.1-20180821, v3.0.0, v3.0.0-rc4, v2.12.1, ppc-for-3.0-20180801, v3.0.0-rc3, v3.0.0-rc2, v3.0.0-rc1, ppc-for-3.0-20180716, v3.0.0-rc0, ppc-for-3.0-20180709, ppc-for-3.0-20180703, v2.11.2 |
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35e238c9 |
| 25-Jun-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/kraxel/tags/audio-20180625-pull-request' into staging audio: new timer code for hda codec, fix audio_get_conf_int # gpg: Signature made Mon 25
Merge remote-tracking branch 'remotes/kraxel/tags/audio-20180625-pull-request' into staging audio: new timer code for hda codec, fix audio_get_conf_int # gpg: Signature made Mon 25 Jun 2018 14:12:41 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/audio-20180625-pull-request: audio: Convert use of atoi to qemu_strtoi audio/hda: enable new timer code by default. audio/hda: detect output buffer overruns audio/hda: tweak timer adjust logic audio/hda: turn some dprintfs into trace points audio/hda: create millisecond timers that handle IO Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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7ed14cbf |
| 22-Jun-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2018-06-22' into staging QAPI patches for 2018-06-22 # gpg: Signature made Fri 22 Jun 2018 15:36:22 BST # gpg:
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2018-06-22' into staging QAPI patches for 2018-06-22 # gpg: Signature made Fri 22 Jun 2018 15:36:22 BST # gpg: using RSA key 3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2018-06-22: MAINTAINERS: Update QAPI stanza for commit fb0bc835e56 qapi/introspect: Eliminate pointless variable in .visit_end() Revert commit d4e5ec877ca qapi: Open files with encoding='utf-8' qapi: remove empty flat union branches and types qapi: allow empty branches in flat unions tests: Add QDict clone-flatten test qdict: Make qdict_flatten() shallow-clone-friendly qapi/events: generate event enum in main module qapi/visit: remove useless prefix argument Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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5fce3122 |
| 22-Jun-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180622' into staging target-arm queue: * hw/intc/arm_gicv3: fix wrong values when reading IPRIORITYR * target/
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180622' into staging target-arm queue: * hw/intc/arm_gicv3: fix wrong values when reading IPRIORITYR * target/arm: fix read of freed memory in kvm_arm_machine_init_done() * virt: support up to 512 CPUs * virt: support 256MB ECAM PCI region (for more PCI devices) * xlnx-zynqmp: Use Cortex-R5F, not Cortex-R5 * mps2-tz: Implement and use the TrustZone Memory Protection Controller * target/arm: enforce alignment checking for v6M cores * xen: Don't use memory_region_init_ram_nomigrate() in pci_assign_dev_load_option_rom() * vl.c: Don't zero-initialize statics for serial_hds # gpg: Signature made Fri 22 Jun 2018 13:56:00 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180622: (28 commits) xen: Don't use memory_region_init_ram_nomigrate() in pci_assign_dev_load_option_rom() vl.c: Don't zero-initialize statics for serial_hds target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline target/arm: Introduce ARM_FEATURE_M_MAIN hw/arm/mps2-tz.c: Instantiate MPCs hw/arm/iotkit: Wire up MPC interrupt lines hw/arm/iotkit: Instantiate MPC hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUS hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate hw/misc/tz-mpc.c: Implement correct blocked-access behaviour hw/misc/tz-mpc.c: Implement registers hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller xlnx-zynqmp: Swap Cortex-R5 for Cortex-R5F target-arm: Add the Cortex-R5F hw/arm/virt: Increase max_cpus to 512 hw/arm/virt: Use 256MB ECAM region by default hw/arm/virt: Add virt-3.0 machine type hw/arm/virt: Add a new 256MB ECAM region hw/arm/virt: Register two redistributor regions when necessary hw/arm/virt-acpi-build: Advertise one or two GICR structures ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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c52e53f4 |
| 22-Jun-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.0-20180622' into staging ppc patch queue 2018-06-22 Another assorted patch of patches for ppc and spapr. * Rewor
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-3.0-20180622' into staging ppc patch queue 2018-06-22 Another assorted patch of patches for ppc and spapr. * Rework of guest pagesize handling for ppc, which avoids guest visibly different behaviour between accelerators * A number of Pnv cleanups, working towards more complete POWER9 support * Migration of VPA data, a significant bugfix # gpg: Signature made Fri 22 Jun 2018 05:23:16 BST # gpg: using RSA key 6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-3.0-20180622: (23 commits) spapr: Don't rewrite mmu capabilities in KVM mode spapr: Limit available pagesizes to provide a consistent guest environment target/ppc: Add ppc_hash64_filter_pagesizes() spapr: Use maximum page size capability to simplify memory backend checking spapr: Maximum (HPT) pagesize property pseries: Update SLOF firmware image to qemu-slof-20180621 target/ppc: Add missing opcode for icbt on PPC440 ppc4xx_i2c: Implement directcntl register ppc4xx_i2c: Remove unimplemented sdata and intr registers sm501: Fix hardware cursor color conversion fpu_helper.c: fix helper_fpscr_clrbit() function spapr: remove unused spapr_irq routines spapr: split the IRQ allocation sequence target/ppc: Add kvmppc_hpt_needs_host_contiguous_pages() helper spapr: Add cpu_apply hook to capabilities spapr: Compute effective capability values earlier target/ppc: Allow cpu compatiblity checks based on type, not instance ppc/pnv: consolidate the creation of the ISA bus device tree ppc/pnv: introduce Pnv8Chip and Pnv9Chip models spapr_cpu_core: migrate VPA related state ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: ppc-for-3.0-20180622 |
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77864267 |
| 18-Jun-2018 |
Cédric Le Goater <clg@kaod.org> |
ppc/pnv: introduce Pnv8Chip and Pnv9Chip models It introduces a base PnvChip class from which the specific processor chip classes, Pnv8Chip and Pnv9Chip, inherit. Each of them needs to
ppc/pnv: introduce Pnv8Chip and Pnv9Chip models It introduces a base PnvChip class from which the specific processor chip classes, Pnv8Chip and Pnv9Chip, inherit. Each of them needs to define an init and a realize routine which will create the controllers of the target processor. For the moment, the base PnvChip class handles the XSCOM bus and the cores. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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Revision tags: ppc-for-3.0-20180618 |
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04026890 |
| 15-Jun-2018 |
Cédric Le Goater <clg@kaod.org> |
ppc/pnv: introduce a new isa_create() operation to the chip model This moves the details of the ISA bus creation under the LPC model but more important, the new PnvChip operation will le
ppc/pnv: introduce a new isa_create() operation to the chip model This moves the details of the ISA bus creation under the LPC model but more important, the new PnvChip operation will let us choose the chip class to use when we introduce the different chip classes for Power9 and Power8. It hides away the processor chip controllers from the machine. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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d35aefa9 |
| 15-Jun-2018 |
Cédric Le Goater <clg@kaod.org> |
ppc/pnv: introduce a new intc_create() operation to the chip model On Power9, the thread interrupt presenter has a different type and is linked to the chip owning the cores. Sig
ppc/pnv: introduce a new intc_create() operation to the chip model On Power9, the thread interrupt presenter has a different type and is linked to the chip owning the cores. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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Revision tags: ppc-for-3.0-20180612, ppc-for-2.13-20180504, ppc-for-2.13-20180427, v2.12.0, v2.12.0-rc4, v2.12.0-rc3, ppc-for-2.12-20180410, v2.12.0-rc2, v2.12.0-rc1, v2.12.0-rc0, ppc-for-2.12-20180319, ppc-for-2.12-20180315, ppc-for-2.12-20180306, ppc-for-2.12-20180302, ppc-for-2.12-20180216, v2.11.1, ppc-for-2.12-20180212, ppc-for-2.12-20180129 |
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82de978a |
| 24-Jan-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/xtensa/tags/20180122-xtensa' into staging target/xtensa updates: - make mini-bootloader independent of the initial CPU state; - add noMMU X
Merge remote-tracking branch 'remotes/xtensa/tags/20180122-xtensa' into staging target/xtensa updates: - make mini-bootloader independent of the initial CPU state; - add noMMU XTFPGA variants; - add two noMMU cores: de212 and sample_controller; - fix issues reported by coverity against xtensa translator and disassembler. # gpg: Signature made Mon 22 Jan 2018 20:00:01 GMT # gpg: using RSA key 0x51F9CC91F83FA044 # gpg: Good signature from "Max Filippov <filippov@cadence.com>" # gpg: aka "Max Filippov <max.filippov@cogentembedded.com>" # gpg: aka "Max Filippov <jcmvbkbc@gmail.com>" # Primary key fingerprint: 2B67 854B 98E5 327D CDEB 17D8 51F9 CC91 F83F A044 * remotes/xtensa/tags/20180122-xtensa: target/xtensa: disas/xtensa: fix coverity warnings target/xtensa: add sample_controller core target/xtensa: allow different default CPU for MMU/noMMU target/xtensa: add de212 core hw/xtensa/xtfpga: support noMMU cores hw/xtensa/xtfpga: extract flash configuration hw/xtensa: extract xtensa_create_memory_regions target/xtensa: fix default sysrom/sysram addresses hw/xtensa/xtfpga: clean up function/structure names hw/xtensa/xtfpga: rewrite mini bootloader Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: ppc-for-2.12-20180121, ppc-for-2.12-20180119 |
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b4d6ed1c |
| 18-Jan-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-01-17' into staging pull-nbd-2018-01-17 - Vladimir Sementsov-Ogievskiy/Eric Blake: 0/6 NBD server refactoring
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-01-17' into staging pull-nbd-2018-01-17 - Vladimir Sementsov-Ogievskiy/Eric Blake: 0/6 NBD server refactoring # gpg: Signature made Thu 18 Jan 2018 02:21:55 GMT # gpg: using RSA key 0xA7A16B4A2527436A # gpg: Good signature from "Eric Blake <eblake@redhat.com>" # gpg: aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" # gpg: aka "[jpeg image of size 6874]" # Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A * remotes/ericb/tags/pull-nbd-2018-01-17: nbd/server: structurize option reply sending nbd/server: Add helper functions for parsing option payload nbd/server: Add va_list form of nbd_negotiate_send_rep_err() nbd/server: Better error for NBD_OPT_EXPORT_NAME failure nbd/server: refactor negotiation functions parameters nbd/server: Hoist nbd_reject_length() earlier Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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5cad8ca5 |
| 18-Jan-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging x86 queue, 2018-01-17 Highlight: new CPU models that expose CPU features that guests can use t
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging x86 queue, 2018-01-17 Highlight: new CPU models that expose CPU features that guests can use to mitigate CVE-2017-5715 (Spectre variant #2). # gpg: Signature made Thu 18 Jan 2018 02:00:03 GMT # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-pull-request: i386: Add EPYC-IBPB CPU model i386: Add new -IBRS versions of Intel CPU models i386: Add FEAT_8000_0008_EBX CPUID feature word i386: Add spec-ctrl CPUID bit i386: Add support for SPEC_CTRL MSR i386: Change X86CPUDefinition::model_id to const char* target/i386: add clflushopt to "Skylake-Server" cpu model pc: add 2.12 machine types Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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6e03cc5c |
| 18-Jan-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.12-20180117' into staging ppc patch queue 2017-01-17 Another pull request for ppc related patches. The most interesting
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.12-20180117' into staging ppc patch queue 2017-01-17 Another pull request for ppc related patches. The most interesting thing here is the new capabilities framework for the pseries machine type. This gives us better handling of several existing incompatibilities between TCG, PR and HV KVM, as well as new ones that arise with POWER9. Further, it will allow reasonable handling of the advertisement of features necessary to mitigate the recent CVEs (Spectre and Meltdown). In addition there's: * Improvide handling of different "vsmt" modes * Significant enhancements to the "pnv" machine type * Assorted other bugfixes # gpg: Signature made Wed 17 Jan 2018 02:21:50 GMT # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.12-20180117: (22 commits) target-ppc: Fix booke206 tlbwe TLB instruction target/ppc: add support for POWER9 HILE ppc/pnv: change initrd address ppc/pnv: fix XSCOM core addressing on POWER9 ppc/pnv: introduce pnv*_is_power9() helpers ppc/pnv: change core mask for POWER9 ppc/pnv: use POWER9 DD2 processor tests/boot-serial-test: fix powernv support ppc/pnv: Update skiboot firmware image spapr: Adjust default VSMT value for better migration compatibility spapr: Allow some cases where we can't set VSMT mode in the kernel target/ppc: Clarify compat mode max_threads value ppc: Change Power9 compat table to support at most 8 threads/core spapr: Remove unnecessary 'options' field from sPAPRCapabilityInfo hw/ppc/spapr_caps: Rework spapr_caps to use uint8 internal representation spapr: Handle Decimal Floating Point (DFP) as an optional capability spapr: Handle VMX/VSX presence as an spapr capability flag target/ppc: Clean up probing of VMX, VSX and DFP availability on KVM spapr: Validate capabilities on migration spapr: Treat Hardware Transactional Memory (HTM) as an optional capability ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: ppc-for-2.12-20180117 |
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c035851a |
| 15-Jan-2018 |
Cédric Le Goater <clg@kaod.org> |
ppc/pnv: fix XSCOM core addressing on POWER9 The XSCOM base address of the core chiplet was wrongly calculated. Use the OPAL macros to fix that and do a couple of renames. Signe
ppc/pnv: fix XSCOM core addressing on POWER9 The XSCOM base address of the core chiplet was wrongly calculated. Use the OPAL macros to fix that and do a couple of renames. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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b3b066e9 |
| 15-Jan-2018 |
Cédric Le Goater <clg@kaod.org> |
ppc/pnv: introduce pnv*_is_power9() helpers These are useful when instantiating device models which are shared between the POWER8 and the POWER9 processor families. Signed-off-b
ppc/pnv: introduce pnv*_is_power9() helpers These are useful when instantiating device models which are shared between the POWER8 and the POWER9 processor families. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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acc95bc8 |
| 11-Jan-2018 |
Michael S. Tsirkin <mst@redhat.com> |
Merge remote-tracking branch 'origin/master' into HEAD Resolve conflicts around apb. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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997eba28 |
| 11-Jan-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180111' into staging target-arm queue: * add aarch64_be linux-user target * Virt: ACPI: fix qemu assert due to
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20180111' into staging target-arm queue: * add aarch64_be linux-user target * Virt: ACPI: fix qemu assert due to re-assigned table data address * imx_fec: various bug fixes and cleanups * hw/timer/pxa2xx_timer: replace hw_error() -> qemu_log_mask() * hw/sd/pxa2xx_mmci: add read/write() trace events * linux-user/arm/nwfpe: Check coprocessor number for FPA emulation * target/arm: Make disas_thumb2_insn() generate its own UNDEF exceptions * hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI * hw/intc/arm_gic: reserved register addresses are RAZ/WI # gpg: Signature made Thu 11 Jan 2018 13:37:25 GMT # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180111: (26 commits) hw/intc/arm_gic: reserved register addresses are RAZ/WI hw/intc/arm_gicv3: Make reserved register addresses RAZ/WI target/arm: Make disas_thumb2_insn() generate its own UNDEF exceptions linux-user/arm/nwfpe: Check coprocessor number for FPA emulation hw/sd/pxa2xx_mmci: add read/write() trace events hw/timer/pxa2xx_timer: replace hw_error() -> qemu_log_mask() imx_fec: Reserve full FSL_IMX25_FEC_SIZE page for the register file imx_fec: Fix a typo in imx_enet_receive() imx_fec: Use correct length for packet size imx_fec: Add support for multiple Tx DMA rings imx_fec: Emulate SHIFT16 in ENETx_RACC imx_fec: Use MIN instead of explicit ternary operator imx_fec: Use ENET_FTRL to determine truncation length imx_fec: Move Tx frame buffer away from the stack imx_fec: Change queue flushing heuristics imx_fec: Refactor imx_eth_enable_rx() imx_fec: Do not link to netdev Virt: ACPI: fix qemu assert due to re-assigned table data address target/arm: Fix stlxp for aarch64_be linux-user: Activate armeb handler registration ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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e890966d |
| 11-Jan-2018 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.12-20180111' into staging ppc patch queue 2018-01-11 This pull request supersedes ppc-for-2.12-20180108 and several befo
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.12-20180111' into staging ppc patch queue 2018-01-11 This pull request supersedes ppc-for-2.12-20180108 and several before it. The earlier pull request included a patch which exposed a bug in the ARM TCG backend. I've pulled that out and will repost once the ARM bug is fixed (a patch has been posted by Richard Henderson). Higlights from this series: * SLOF update * Several new devices for embedded platforms * Fix to correctly set compatiblity mode for hotplugged CPUs * dtc compile fix for older MacOS versions # gpg: Signature made Thu 11 Jan 2018 04:58:11 GMT # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.12-20180111: spapr: Correct compatibility mode setting for hotplugged CPUs hw/ppc: Remove the deprecated spapr-pci-vfio-host-bridge device Update dtc to fix compilation problem on Mac OS 10.6 target/ppc: more use of the PPC_*() macros ppc/pnv: change powernv_ prefix to pnv_ for overall naming consistency hw/ide: Emulate SiI3112 SATA controller spapr_pci: use warn_report() ppc4xx_i2c: Implement basic I2C functions sm501: Add some more unimplemented registers sm501: Add panel hardware cursor registers also to read function pseries: Update SLOF firmware image to qemu-slof-20171214 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: ppc-for-2.12-20180111, ppc-for-2.12-20180108, ppc-for-2.12-20180103, ppc-for-2.12-20171219, v2.10.2 |
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b168a138 |
| 15-Dec-2017 |
Cédric Le Goater <clg@kaod.org> |
ppc/pnv: change powernv_ prefix to pnv_ for overall naming consistency The 'pnv' prefix is now used for all and the routines populating the device tree start with 'pnv_dt'. The handler o
ppc/pnv: change powernv_ prefix to pnv_ for overall naming consistency The 'pnv' prefix is now used for all and the routines populating the device tree start with 'pnv_dt'. The handler of the PnvXScomInterface is also renamed to 'dt_xscom' which should reflect that it is populating the device tree under the 'xscom@' node of the chip. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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Revision tags: ppc-for-2.12-20171215, v2.11.0, v2.11.0-rc5, v2.11.0-rc4, ppc-for-2.11-20171205, ppc-for-2.11-20171204, v2.11.0-rc3, ppc-for-2.11-20171127, ppc-for-2.11-20171122, v2.11.0-rc2, ppc-for-2.11-20171120, v2.11.0-rc1, ppc-for-2.11-20171114, ppc-for-2.11-20171108, v2.11.0-rc0 |
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a8b392ac |
| 19-Oct-2017 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging * TCG 8-byte atomic accesses bugfix (Andrew) * Report disk rotation rate (Daniel) * Report invalid scsi-
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging * TCG 8-byte atomic accesses bugfix (Andrew) * Report disk rotation rate (Daniel) * Report invalid scsi-disk block size configuration (Mark) * KVM and memory API MemoryListener fixes (David, Maxime, Peter Xu) * x86 CPU hotplug crash fix (Igor) * Load/store API documentation (Peter Maydell) * Small fixes by myself and Thomas * qdev DEVICE_DELETED deferral (Michael) # gpg: Signature made Wed 18 Oct 2017 10:56:24 BST # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (29 commits) scsi: reject configurations with logical block size > physical block size qdev: defer DEVICE_DEL event until instance_finalize() Revert "qdev: Free QemuOpts when the QOM path goes away" qdev: store DeviceState's canonical path to use when unparenting qemu-pr-helper: use new libmultipath API watch_mem_write: implement 8-byte accesses notdirty_mem_write: implement 8-byte accesses memory: reuse section_from_flat_range() kvm: simplify kvm_align_section() kvm: region_add and region_del is not called on updates kvm: fix error message when failing to unregister slot kvm: tolerate non-existing slot for log_start/log_stop/log_sync kvm: fix alignment of ram address memory: call log_start after region_add target/i386: trap on instructions longer than >15 bytes target/i386: introduce x86_ld*_code tco: add trace events docs/devel/loads-stores.rst: Document our various load and store APIs nios2: define tcg_env build: remove CONFIG_LIBDECNUMBER ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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f2a48d69 |
| 19-Oct-2017 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/riku/tags/pull-linux-user-20171018' into staging Linux-user updates for Qemu 2.11 # gpg: Signature made Wed 18 Oct 2017 13:20:14 BST # gpg:
Merge remote-tracking branch 'remotes/riku/tags/pull-linux-user-20171018' into staging Linux-user updates for Qemu 2.11 # gpg: Signature made Wed 18 Oct 2017 13:20:14 BST # gpg: using RSA key 0xB44890DEDE3C9BC0 # gpg: Good signature from "Riku Voipio <riku.voipio@iki.fi>" # gpg: aka "Riku Voipio <riku.voipio@linaro.org>" # Primary key fingerprint: FF82 03C8 C391 98AE 0581 41EF B448 90DE DE3C 9BC0 * remotes/riku/tags/pull-linux-user-20171018: linux-user: Fix TARGET_MTIOCTOP/MTIOCGET/MTIOCPOS values linux-user/main: support dfilter linux-user: Fix target FS_IOC_GETFLAGS and FS_IOC_SETFLAGS numbers linux-user/sh4: Reduce TARGET_VIRT_ADDR_SPACE_BITS to 31 linux-user: Tidy and enforce reserved_va initialization tcg: Fix off-by-one in assert in page_set_flags linux-user: Allow -R values up to 0xffff0000 for 32-bit ARM guests linux-user: remove duplicate break in syscall target/m68k,linux-user: manage FP registers in ucontext linux-user: fix O_TMPFILE handling Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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ba6f0fc2 |
| 19-Oct-2017 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/kraxel/tags/opengl-20171017-pull-request' into staging ui: opengl updates for dma-buf support. # gpg: Signature made Tue 17 Oct 2017 12:13:36 B
Merge remote-tracking branch 'remotes/kraxel/tags/opengl-20171017-pull-request' into staging ui: opengl updates for dma-buf support. # gpg: Signature made Tue 17 Oct 2017 12:13:36 BST # gpg: using RSA key 0x4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/opengl-20171017-pull-request: egl-headless: add dmabuf support egl-helpers: add egl_texture_blit and egl_texture_blend egl-helpers: add dmabuf import support opengl: add flipping vertex shader opengl: move shader init from console-gl.c to shader.c console: add support for dmabufs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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73b733e6 |
| 19-Oct-2017 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/kraxel/tags/vga-20171017-pull-request' into staging cirrus: bugfixes, with some vga cleanups. # gpg: Signature made Tue 17 Oct 2017 09:24:37 BS
Merge remote-tracking branch 'remotes/kraxel/tags/vga-20171017-pull-request' into staging cirrus: bugfixes, with some vga cleanups. # gpg: Signature made Tue 17 Oct 2017 09:24:37 BST # gpg: using RSA key 0x4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/vga-20171017-pull-request: cirrus: fix oob access in mode4and5 write functions vga: add ram_addr_t cast vga: handle cirrus vbe mode wraparounds. vga: drop line_offset variable Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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861cd431 |
| 17-Oct-2017 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.11-20171017' into staging ppc patch queue 2017-10-17 Here's the currently accumulated set of ppc patches for qemu.
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.11-20171017' into staging ppc patch queue 2017-10-17 Here's the currently accumulated set of ppc patches for qemu. * The biggest set here is the ppc parts of Igor Mammedov's cleanups to cpu model handling * The above also includes a generic patches which are required as prerequisites for the ppc parts. They don't seem to have been merged by Eduardo yet, so I hope they're ok to include here. * Apart from that it's basically just assorted bug fixes and cleanups # gpg: Signature made Tue 17 Oct 2017 05:20:03 BST # gpg: using RSA key 0x6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-2.11-20171017: (34 commits) spapr_cpu_core: rewrite machine type sanity check spapr_pci: fail gracefully with non-pseries machine types spapr: Correct RAM size calculation for HPT resizing ppc: pnv: consolidate type definitions and batch register them ppc: pnv: drop PnvChipClass::cpu_model field ppc: pnv: define core types statically ppc: pnv: drop PnvCoreClass::cpu_oc field ppc: pnv: normalize core/chip type names ppc: pnv: use generic cpu_model parsing ppc: spapr: use generic cpu_model parsing ppc: move ppc_cpu_lookup_alias() before its first user ppc: spapr: use cpu model names as tcg defaults instead of aliases ppc: spapr: register 'host' core type along with the rest of core types ppc: spapr: use cpu type name directly ppc: spapr: define core types statically ppc: move '-cpu foo,compat=xxx' parsing into ppc_cpu_parse_featurestr() ppc: spapr: replace ppc_cpu_parse_features() with cpu_parse_cpu_model() ppc: 40p/prep: replace cpu_model with cpu_type ppc: virtex-ml507: replace cpu_model with cpu_type ppc: replace cpu_model with cpu_type on ref405ep,taihu boards ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Revision tags: ppc-for-2.11-20171017 |
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40abf43f |
| 09-Oct-2017 |
Igor Mammedov <imammedo@redhat.com> |
ppc: pnv: drop PnvChipClass::cpu_model field deduce core type directly from chip type instead of maintaining type mapping in PnvChipClass::cpu_model. Signed-off-by: Igor Mammedo
ppc: pnv: drop PnvChipClass::cpu_model field deduce core type directly from chip type instead of maintaining type mapping in PnvChipClass::cpu_model. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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7fd544d8 |
| 09-Oct-2017 |
Igor Mammedov <imammedo@redhat.com> |
ppc: pnv: normalize core/chip type names typically for cpus/core type names following convention is used new_type_prefix-superclass_typename make PNV core/chip to follow
ppc: pnv: normalize core/chip type names typically for cpus/core type names following convention is used new_type_prefix-superclass_typename make PNV core/chip to follow common convention. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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4a12c699 |
| 09-Oct-2017 |
Igor Mammedov <imammedo@redhat.com> |
ppc: pnv: use generic cpu_model parsing use common cpu_model prasing in vl.c and set default cpu_model using generic MachineClass::default_cpu_type. Beside of switching to gener
ppc: pnv: use generic cpu_model parsing use common cpu_model prasing in vl.c and set default cpu_model using generic MachineClass::default_cpu_type. Beside of switching to generic infrastructure it solves several issues. * ppc_cpu_class_by_name() is used to deal with lower/upper case and alias translations into actual cpu type, which fixes '-M powernv -cpu power8' and '-M powernv -cpu power9_v1.0' usecases which error out with: 'invalid CPU model 'FOO' for powernv machine' * allows to switch to lower-case typenames in pnv chip/core name (by convention typnames should be lower-case) * replace aliased names /power8, power9, .../ with exact cpu model names (i.e. typenames should be stable but aliases might decide to point to other cpu model withi family or changed by kvm). It will also help to simplify pnv_chip/core code and get rid of dependency on cpu_model parsing. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> [dwg: Updated to make DD2.0 as default POWER9 chip] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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