1 /* 2 * QEMU PowerPC PowerNV various definitions 3 * 4 * Copyright (c) 2014-2016 BenH, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef _PPC_PNV_H 20 #define _PPC_PNV_H 21 22 #include "hw/boards.h" 23 #include "hw/sysbus.h" 24 #include "hw/ipmi/ipmi.h" 25 #include "hw/ppc/pnv_lpc.h" 26 #include "hw/ppc/pnv_psi.h" 27 #include "hw/ppc/pnv_occ.h" 28 29 #define TYPE_PNV_CHIP "powernv-chip" 30 #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) 31 #define PNV_CHIP_CLASS(klass) \ 32 OBJECT_CLASS_CHECK(PnvChipClass, (klass), TYPE_PNV_CHIP) 33 #define PNV_CHIP_GET_CLASS(obj) \ 34 OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) 35 36 typedef enum PnvChipType { 37 PNV_CHIP_POWER8E, /* AKA Murano (default) */ 38 PNV_CHIP_POWER8, /* AKA Venice */ 39 PNV_CHIP_POWER8NVL, /* AKA Naples */ 40 PNV_CHIP_POWER9, /* AKA Nimbus */ 41 } PnvChipType; 42 43 typedef struct PnvChip { 44 /*< private >*/ 45 SysBusDevice parent_obj; 46 47 /*< public >*/ 48 uint32_t chip_id; 49 uint64_t ram_start; 50 uint64_t ram_size; 51 52 uint32_t nr_cores; 53 uint64_t cores_mask; 54 void *cores; 55 56 hwaddr xscom_base; 57 MemoryRegion xscom_mmio; 58 MemoryRegion xscom; 59 AddressSpace xscom_as; 60 MemoryRegion icp_mmio; 61 62 PnvLpcController lpc; 63 PnvPsi psi; 64 PnvOCC occ; 65 } PnvChip; 66 67 typedef struct PnvChipClass { 68 /*< private >*/ 69 SysBusDeviceClass parent_class; 70 71 /*< public >*/ 72 const char *cpu_model; 73 PnvChipType chip_type; 74 uint64_t chip_cfam_id; 75 uint64_t cores_mask; 76 77 hwaddr xscom_base; 78 hwaddr xscom_core_base; 79 80 uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id); 81 } PnvChipClass; 82 83 #define TYPE_PNV_CHIP_POWER8E TYPE_PNV_CHIP "-power8e_v2.1" 84 #define PNV_CHIP_POWER8E(obj) \ 85 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8E) 86 87 #define TYPE_PNV_CHIP_POWER8 TYPE_PNV_CHIP "-power8_v2.0" 88 #define PNV_CHIP_POWER8(obj) \ 89 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8) 90 91 #define TYPE_PNV_CHIP_POWER8NVL TYPE_PNV_CHIP "-power8nvl_v1.0" 92 #define PNV_CHIP_POWER8NVL(obj) \ 93 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER8NVL) 94 95 #define TYPE_PNV_CHIP_POWER9 TYPE_PNV_CHIP "-power9_v2.0" 96 #define PNV_CHIP_POWER9(obj) \ 97 OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP_POWER9) 98 99 /* 100 * This generates a HW chip id depending on an index, as found on a 101 * two socket system with dual chip modules : 102 * 103 * 0x0, 0x1, 0x10, 0x11 104 * 105 * 4 chips should be the maximum 106 * 107 * TODO: use a machine property to define the chip ids 108 */ 109 #define PNV_CHIP_HWID(i) ((((i) & 0x3e) << 3) | ((i) & 0x1)) 110 111 /* 112 * Converts back a HW chip id to an index. This is useful to calculate 113 * the MMIO addresses of some controllers which depend on the chip id. 114 */ 115 #define PNV_CHIP_INDEX(chip) \ 116 (((chip)->chip_id >> 2) * 2 + ((chip)->chip_id & 0x3)) 117 118 #define TYPE_POWERNV_MACHINE MACHINE_TYPE_NAME("powernv") 119 #define POWERNV_MACHINE(obj) \ 120 OBJECT_CHECK(PnvMachineState, (obj), TYPE_POWERNV_MACHINE) 121 122 typedef struct PnvMachineState { 123 /*< private >*/ 124 MachineState parent_obj; 125 126 uint32_t initrd_base; 127 long initrd_size; 128 129 uint32_t num_chips; 130 PnvChip **chips; 131 132 ISABus *isa_bus; 133 uint32_t cpld_irqstate; 134 135 IPMIBmc *bmc; 136 Notifier powerdown_notifier; 137 } PnvMachineState; 138 139 #define PNV_FDT_ADDR 0x01000000 140 #define PNV_TIMEBASE_FREQ 512000000ULL 141 142 /* 143 * BMC helpers 144 */ 145 void pnv_bmc_populate_sensors(IPMIBmc *bmc, void *fdt); 146 void pnv_bmc_powerdown(IPMIBmc *bmc); 147 148 /* 149 * POWER8 MMIO base addresses 150 */ 151 #define PNV_XSCOM_SIZE 0x800000000ull 152 #define PNV_XSCOM_BASE(chip) \ 153 (chip->xscom_base + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE) 154 155 /* 156 * XSCOM 0x20109CA defines the ICP BAR: 157 * 158 * 0:29 : bits 14 to 43 of address to define 1 MB region. 159 * 30 : 1 to enable ICP to receive loads/stores against its BAR region 160 * 31:63 : Constant 0 161 * 162 * Usually defined as : 163 * 164 * 0xffffe00200000000 -> 0x0003ffff80000000 165 * 0xffffe00600000000 -> 0x0003ffff80100000 166 * 0xffffe02200000000 -> 0x0003ffff80800000 167 * 0xffffe02600000000 -> 0x0003ffff80900000 168 */ 169 #define PNV_ICP_SIZE 0x0000000000100000ull 170 #define PNV_ICP_BASE(chip) \ 171 (0x0003ffff80000000ull + (uint64_t) PNV_CHIP_INDEX(chip) * PNV_ICP_SIZE) 172 173 174 #define PNV_PSIHB_SIZE 0x0000000000100000ull 175 #define PNV_PSIHB_BASE(chip) \ 176 (0x0003fffe80000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * PNV_PSIHB_SIZE) 177 178 #define PNV_PSIHB_FSP_SIZE 0x0000000100000000ull 179 #define PNV_PSIHB_FSP_BASE(chip) \ 180 (0x0003ffe000000000ull + (uint64_t)PNV_CHIP_INDEX(chip) * \ 181 PNV_PSIHB_FSP_SIZE) 182 183 #endif /* _PPC_PNV_H */ 184