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7a5951f6 |
| 22-Dec-2022 |
Markus Armbruster <armbru@redhat.com> |
include: Include headers where needed
A number of headers neglect to include everything they need. They compile only if the headers they need are already included from elsewhere. Fix that.
Signed
include: Include headers where needed
A number of headers neglect to include everything they need. They compile only if the headers they need are already included from elsewhere. Fix that.
Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20221222120813.727830-3-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Revision tags: v6.2.0, v6.1.0 |
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a68694cd |
| 14-Sep-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200914' into staging EDK2 firmware: Adopt the edk2-stable202008 release Note from Laszlo Ersek [1] while address
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/edk2-next-20200914' into staging EDK2 firmware: Adopt the edk2-stable202008 release Note from Laszlo Ersek [1] while addressing LP#1852196 [2]: Consume the following upstream edk2 releases: https://github.com/tianocore/edk2/releases/tag/edk2-stable201908 https://github.com/tianocore/edk2/releases/tag/edk2-stable201911 https://github.com/tianocore/edk2/releases/tag/edk2-stable202002 https://github.com/tianocore/edk2/releases/tag/edk2-stable202005 https://github.com/tianocore/edk2/releases/tag/edk2-stable202008 Worth mentioning (in random order): - various CVE fixes (see [2] and shortlog) - OpenSSL-1.1.1g - UEFI HTTPS Boot for ARM/AARCH64 - TPM2 for ARM/AARCH64 - VCPU hotplug with SMI - support for Linux v5.7+ initrd and mixed mode loading - Fusion-MPT SCSI driver in OVMF - VMware PVSCSI driver in OVMF - PXEv4 / PXEv6 boot possible to disable on the QEMU command line - SEV-ES support The IA32 and X64 binaries are now smaller -- the reason is that Laszlo built them with DevToolSet 9 (gcc-9) on RHEL7, and so this is the first time they've undergone LTO (with the GCC5 edk2 toolchain settings). CI jobs results: https://gitlab.com/philmd/qemu/-/pipelines/189394120 https://travis-ci.org/github/philmd/qemu/builds/726842542 https://app.shippable.com/github/philmd/qemu/runs/866/summary/console [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg738173.html [2] https://bugs.launchpad.net/qemu/+bug/1852196 # gpg: Signature made Mon 14 Sep 2020 08:15:37 BST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * remotes/philmd-gitlab/tags/edk2-next-20200914: tests: acpi: update "virt/SSDT.memhp" for edk2-stable202008 pc-bios: update the README file with edk2-stable202008 information pc-bios: refresh edk2 build artifacts for edk2-stable202008 roms/Makefile.edk2: enable new ARM/AARCH64 flags up to edk2-stable202008 roms/Makefile.edk2: complete replacing TPM2*_ENABLE macros roms/edk2: update submodule from edk2-stable201905 to edk2-stable202008 tests: acpi: tolerate "virt/SSDT.memhp" mismatch temporarily roms/Makefile.edk2: prepare for replacing TPM2*_ENABLE macros roms/efirom, tests/uefi-test-tools: update edk2's own submodules first Makefile: remove obsolete edk2 exception from "clean" rule Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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95f21798 |
| 14-Sep-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/mdroth/tags/qga-pull-2020-09-12-tag' into staging patch queue for qemu-ga * add guest-get-devices for reporting virtio devices (w32-only) *
Merge remote-tracking branch 'remotes/mdroth/tags/qga-pull-2020-09-12-tag' into staging patch queue for qemu-ga * add guest-get-devices for reporting virtio devices (w32-only) * extend guest-get-fsinfo to support non-PCI virtio disk controllers # gpg: Signature made Mon 14 Sep 2020 02:53:51 BST # gpg: using RSA key CEACC9E15534EBABB82D3FA03353C9CEF108B584 # gpg: issuer "mdroth@linux.vnet.ibm.com" # gpg: Good signature from "Michael Roth <flukshun@gmail.com>" [full] # gpg: aka "Michael Roth <mdroth@utexas.edu>" [full] # gpg: aka "Michael Roth <mdroth@linux.vnet.ibm.com>" [full] # Primary key fingerprint: CEAC C9E1 5534 EBAB B82D 3FA0 3353 C9CE F108 B584 * remotes/mdroth/tags/qga-pull-2020-09-12-tag: qga: add command guest-get-devices for reporting VirtIO devices qga/commands-posix: Support fsinfo for non-PCI virtio devices, too qga/commands-posix: Move the udev code from the pci to the generic function qga/commands-posix: Rework build_guest_fsinfo_for_real_device() function Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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#
f00f57f3 |
| 13-Sep-2020 |
Peter Maydell <peter.maydell@linaro.org> |
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging This PR includes multiple fixes and features for RISC-V: - Fixes a bug in printing trap ca
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200910' into staging This PR includes multiple fixes and features for RISC-V: - Fixes a bug in printing trap causes - Allows 16-bit writes to the SiFive test device. This fixes the failure to reboot the RISC-V virt machine - Support for the Microchip PolarFire SoC and Icicle Kit - A reafactor of RISC-V code out of hw/riscv # gpg: Signature made Thu 10 Sep 2020 19:08:06 BST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20200910: (30 commits) hw/riscv: Sort the Kconfig options in alphabetical order hw/riscv: Drop CONFIG_SIFIVE hw/riscv: Always build riscv_hart.c hw/riscv: Move sifive_test model to hw/misc hw/riscv: Move sifive_uart model to hw/char hw/riscv: Move riscv_htif model to hw/char hw/riscv: Move sifive_plic model to hw/intc hw/riscv: Move sifive_clint model to hw/intc hw/riscv: Move sifive_gpio model to hw/gpio hw/riscv: Move sifive_u_otp model to hw/misc hw/riscv: Move sifive_u_prci model to hw/misc hw/riscv: Move sifive_e_prci model to hw/misc hw/riscv: sifive_u: Connect a DMA controller hw/riscv: clint: Avoid using hard-coded timebase frequency hw/riscv: microchip_pfsoc: Hook GPIO controllers hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 hw/net: cadence_gem: Add a new 'phy-addr' property hw/riscv: microchip_pfsoc: Connect a DMA controller hw/dma: Add SiFive platform DMA controller emulation ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org> # Conflicts: # hw/riscv/trace-events
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97ba4223 |
| 31-Aug-2020 |
Bin Meng <bin.meng@windriver.com> |
hw/dma: Add SiFive platform DMA controller emulation Microchip PolarFire SoC integrates a DMA engine that supports: * Independent concurrent DMA transfers using 4 DMA channels * Gene
hw/dma: Add SiFive platform DMA controller emulation Microchip PolarFire SoC integrates a DMA engine that supports: * Independent concurrent DMA transfers using 4 DMA channels * Generation of interrupts on various conditions during execution which is actually an IP reused from the SiFive FU540 chip. This creates a model to support both polling and interrupt modes. Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <1598924352-89526-10-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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